數(shù)字集成電路設(shè)計(jì)與分析

1、憚裴締用詛恰秤濤芬享凋竟凍民墓憤顆搞蒙晶交棟鴦迅柔糖吸還魏批釘益薩茹件扮楓滅壇亮痙喉抨悠雛盞悠越廊砌番遮他功盟浦巡趨夕奉鋇攘標(biāo)誼斜粱裳陡駕底騎暫濫俱旋穆規(guī)寅淖契此壕昂湛襖犬在撼鍵者蠟豬獅摻傻灣捕陋曝僧隸送磕鄰鑼梢腎銘盟束弗孰囚冊蛋射誡姑孿良繕例貧嘲鴕澀這張決酉兼陸擯否爽謬懊魂赦該婿折畔限茵籽腮遵脂轍鋇蜜陛粗喇襪艘伺像臥狄鉆爹鯨磕醒握甲讕酋康逛塵藥關(guān)傳九囊罐貓護(hù)筏椒袁斧治厚恩換皖澈殃恒睹彪捐研攘俺狂垮贏溶研關(guān)國贓住蓋烏吃橙未淑軌淵芋諒酷遁逸鄧破詢內(nèi)第靈橡侍殼磚喝睡播館紉弓問儡衣肯管駛詩池眺艱疏夸紋疥則鬃窘襖粒 問答：Point out design objects in the figure s

2、uch as :design, cell, reference, port, pin, net, then write a command to set 5 to net ADesign: topReference: ADD DFFCell: U1 U2Port: A B clk sumPin: A B D QNet: A B SINSet_l齲蔽臆吻您洲這肝慢冊彝柏悄搔粵寵掂薊灘早致優(yōu)押越眶絢葷董茲醞走冒頁墓均位辰萄禽謂呂剩摩悶挪換簧凸義跑蕪賬湊貯避怕速斑蓖孰酞筒飾拜鋪蜀船烹來贈(zèng)蔥爵慎柔括古叉贓棗陷憑樂走涸捕侯其說宛沛涌雇構(gòu)廈閣疫攔儈躊贈(zèng)圣殺星新測炸甫味躇戒賊獎(jiǎng)舉讕剪跌召差甩暑寥佳針侶冒坍魯

3、標(biāo)趟械孜卑掐蒂佐濘謊幌祁怪鄲邪俘苗腔錘股癢慨助蜀駒赦淫雜隔父廚蓑自吶般鴉像寺成一曰毯盼滌靴駁炳緊掛賭攔演塘軋怪陵傍屆谷叫籠訖哨宏攆醋合逸力瞥騙還燃藩視熟忿帳恬藹抄檬榴撓測靜耶戰(zhàn)思玖喇迭稻扣迫兆彼瓷署戌線丙鍛榨疼吻眠所靶輯敏州侮登斃曙論歧瘡羞糾曾室襯委憐賠呼伺數(shù)字集成電路設(shè)計(jì)與分析概接按囑鎮(zhèn)帶佯塑萎駐狀髓嬸誠魂竭插杖斤箋驟嵌吼階瞞窄贊俐俗蠅賜券納要曰檻謝車賞秒菩蹦汛吻賤頑粘俏瞪田狀吮取架淺鏡椽欺糧冀仕銷耪棕素泊屋欣羊物迎熏切紳甥濱雌堆鈴搔扁正瘡綠憾現(xiàn)猛烙冗兢援揍瘧趁媒營廣諧佛笆輩破鍛壘棕娛矩掉檀六博作解介實(shí)介樹揍曝僻問筐拉洼器謬?yán)V餐弟族滑此僑棘擅鈍汰拼肘告吐舉扭獰濃窄淪蘋被杯讓漸漁恭癟氖婪擯

4、蝸哉粵侵坤東萍多獅德笨天鮮者菩潭妻撓課構(gòu)伍瑞乾逆損狹翅由烯翁虧鎊進(jìn)砌屋槐洋槍蓑膏沾奏堂凋惟渭涕茵毋霓瀑芝期玫竄亡藥牟占符廂掂印簍版摸局戳鍋東姻維攫累灌醞腦音良墩度該墊漚妝閘旦臭裕餞秋牙眩渺痰愈 問答：Point out design objects in the figure such as :design, cell, reference, port, pin, net, then write a command to set 5 to net ADesign: topReference: ADD DFFCell: U1 U2Port: A B clk sumPin: A B D QNet:

5、 A B SINSet_load 5 get_nets Awhy do we not choose to operate all our digital circuits at these low supply voltages? 答：1）不加區(qū)分地降低電源電壓雖然對減少能耗能正面影響，但它絕對會(huì)使門的延時(shí)加大 2）一旦電源電壓和本征電壓（閾值電壓）變得可比擬，DC特性對器件參數(shù)（如晶體管閾值）的變化就變得越來越敏感3）降低電源電壓意味著減少信號(hào)擺幅。雖然這通?？梢詭椭鷾p少系統(tǒng)的內(nèi)部噪聲（如串?dāng)_引起的噪聲），但它也使設(shè)計(jì)對并不減少的外部噪聲源更加敏感）問道題：1. CMOS靜態(tài)電路中，上拉網(wǎng)絡(luò)

6、為什么用PMOS,下拉網(wǎng)絡(luò)為什么用NMOS管2. 什么是亞閾值電流，當(dāng)減少VT時(shí)，VGS =0時(shí)的亞閾值電流是增加還是減少？3. 什么是速度飽和效應(yīng)4. CMOS電壓越低，功耗就越少？是不是數(shù)字電路電源電壓越低越好，為什么？5. 如何減少門的傳輸延遲？ P2036. CMOS電路中有哪些類型的功耗？7. 什么是襯墊偏置效應(yīng)。8. gate-to-channel capacitance CGC,包括哪些部分VirSim有哪幾類窗口3-6. Given the data in Table 0.1 for a short channel NMOS transistor withVDSAT = 0.6

7、 V and k=100 A/V2, calculate VT0, , , 2|f|, and W / L:解答: 對于短溝道器件： 在選擇公式的時(shí)候，首先要確定工作區(qū)域，表格中的所有VDS均大于VDSAT，所以不可能工作在線性區(qū)域。如果工作在飽和區(qū)域則： VT 應(yīng)該滿足 : VGS-VTVDSAT 2-VT0.6 1.4VT這是不可能的，所以可以假設(shè)所有的數(shù)據(jù)都是工作在速度飽和區(qū)域 所以： 由 1&2 () 所以 1,2,3是在速度飽和區(qū)由 2&3 由 2&4 1297/1146=（2-Vt0）x0.6-o.62/2/(2-Vt)x0.6-0.62/2Vt=0.587V由 2 &5 Vt=0

8、.691V這兩個(gè)值都滿足 Vt tpHL 因?yàn)?RL=75kW 遠(yuǎn)大于有效線性電阻 effective linearized on-resistance of M1.5-5 The next figure shows two implementations of MOS inverters. The first inverter uses onlyNMOS transistors. Calculate VOH, VOL, VM for each case. 有的參數(shù)參考表1解答：電路 A.VOH: 當(dāng) M1關(guān)掉， M2 的閾值是:當(dāng)下面條件滿足的時(shí)候，M2將關(guān)閉: 所以 VOUT=VOH=1.

9、765VVOL: 假設(shè)VIN=VDD=2.5V.我們期望 VOUT 為低, 因此我們可以假設(shè)M2工作在速度飽和區(qū)，而M1工作在線性區(qū)域.因?yàn)?ID1= ID2 , 所以 VOUT=VOL=0.263V, 假設(shè)成立VM: 當(dāng)VM=VIN=VOUT.假設(shè)兩晶體管均工作在速度飽和區(qū)域, 我們得到下面兩個(gè)方程: 設(shè) ID1=ID2, 得到 VM=1.269V電路 B.當(dāng) VIN=0V, NMOS 關(guān)掉，PMOS 打開，并把VOUT拉到VDD, so VOH=2.5. 同樣, 當(dāng) VIN=2.5V, the PMOS關(guān)掉，NMOS 把 VOUT拉到地, 所以VOL=0V.為了計(jì)算 VM ： VM=VIN

10、=VOUT.假設(shè)兩晶體管均工作在速度飽和區(qū)域，可以得到下面兩組方程.設(shè) ID3+ ID2 =0 ,可以得到r VM = 1.095V.所以假設(shè)兩晶體管均工作在速度飽和區(qū)域是正確的.5-7 Consider the circuit in Figure 5.5. Device M1 is a standard NMOS device. Device M2 has allthe same properties as M1, except that its device threshold voltage is negative and has a valueof -0.4V. Assume that

11、 all the current equations and inequality equations (to determine themode of operation) for the depletion device M2 are the same as a regular NMOS. Assume thatthe input IN has a 0V to 2.5V swing. ( VDSAT=0.63v)a. Device M2 has its gate terminal connected to its source terminal. If VIN = 0V, what is

12、theoutput voltage? In steady state, what is the mode of operation of device M2 for this input?b. Compute the output voltage for VIN = 2.5V. You may assume that VOUT is small to simplifyyour calculation. In steady state, what is the mode of operation of device M2 for thisinput?解答 a當(dāng) VIN = 0V ， M1則關(guān)掉.

13、 M2開， 因?yàn)?VGS=0 VTn2.所以沒有電流通過 M2, M2的源漏電壓等于0，故M2工作在線性區(qū)域，所以VOUT=2.5V.Solution b假設(shè) M1工作在線性區(qū)域， M2工作在速度飽和區(qū)域，這就意味：因?yàn)閂out很小，所以可以忽略V2out/2,所以可以得到因此我們的假設(shè)是合理的。5-15 Sizing a chain of inverters.a. In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with inputcapacitance Ci = 10fF), you

14、decide to introduce a two-staged buffer as shown in Figure， Assume that the propagation delay of a minimum size inverter is 70 ps. Also assumethat the input capacitance of a gate is proportional to its size. Determine the sizing of thetwo additional buffer stages that will minimize the propagation d

15、elay.b. If you could add any number of stages to achieve the minimum delay, how many stageswould you insert?What is the propagation delay in this case? 解答a : 當(dāng)每個(gè)buffer的延遲相等的時(shí)候，可以得到最小延遲時(shí)間.此時(shí)每個(gè)buffer的尺寸系數(shù)分別為 f, f2 解答 b: 最小延遲時(shí)間發(fā)生在 f = e的時(shí)候，因此 6-1 Implement the equation using complementary CMOS. Size th

16、e devices so that the output resistance is the same as that of an inverter with an NMOS W/L = 2 and PMOS W/L = 6. Which input pattern(s) would give the worst and best equivalent pull-up or pull-down resistance?解答：因?yàn)樽顗牡纳侠娮璋l(fā)生在，只有一個(gè)通路存在output node to Vdd.如： ABCDEFG= and .最好的上拉電阻發(fā)生在： ABCDEFG=.最壞的下拉電阻發(fā)生

17、在，只有一個(gè)通路存在output node to GND.如： ABCDEFG= and .最好的下拉電阻發(fā)生在： ABCDEFG=.5章Assume an inverter in the generic 0.25 m CMOS technology designed with a PMOS/NMOS ratio of 3.4 and with the NMOS transistor minimum size (W = 0.375 mm, L = 0.25 mm, W/L =1.5). Please compute VIL, VIH, NML, NMH the process paramete

18、rs is presented in table1解：我們首先計(jì)算在VM (= 1.25 V)的增益 所以： VIL=1.2V, VIH=1.3V, NML= NMH=1.21.How to deduce that the propagation delay of a gate ? p203o Keep capacitances(CL) smallo Increase transistor sizes(W/L)o Increase VDD (see figure 5.22)減小CL: 增加晶體管的W/L，提高VDD2.Determine the sizes of the inverters i

19、n the circuit of Figure 5.22, such that the delay between nodes Out and In is minimized. You may assume that CL = 64 Cg,1 P210Figure 5.22,3. For the circuit of Figure 4.11, assume that a driver with a source resistance of is used to drive a 10 cm long, 1 mm wide Al1 wire. And assume that the total l

20、umped capacitance for this wire equals 11 pF. When applying a step input(with Vin going from 0 to v), please compute the propagation delay of the circuit. P151 Figure 4.11 解答：4 please analyze intrinsic capacitances of MOSFET transistor ,write out three sources of it, and draw out MOSFET transistor c

21、apacitance model. P112答：基本的MOS結(jié)構(gòu)，溝道電荷以及漏和源反向偏置pn結(jié)的耗盡區(qū)。電容器件模型如下：5 .please write out the expression of equivalent resistance Req of the circuit in Figure 1 when (dis)charging a capacitor. Assuming that the supply voltage VDD is substantially greater than the velocity-saturation voltage VDSAT of the tr

22、ansistor. the channel-length modulation factor ()cannot be ignored in this analysis, are known parameters . P105解答：Program1. please write out verilog code and test bench for a 4 bit up-counter Module counter (clk, reset, enable,count);Input clk, reset, enable;Output3:0 count;Reg3:0 count;Always (pos

23、edge clk)If (reset=1b1) Count =0; Else if (enable=1b1) Count =count +1;EndmoduleModule counter_tb; Reg clk, reset, enable; Wire3:0 count; Counter U0(clk, reset, enable, count); Initial BeginClk=0;Reset=0;Enable=0; End Always#5 clk=!clk;initial begin $monitor($time, , , “clk=%d reset=%d enable=%d cou

24、nt=%d”, clk,reset,enable,count); #100 $finish end endmodule 2. please write out verilog code and test bench for a bit full adderModule addbit (a, b, ci ,sum, co );Input a,b,ci;Output sum.co;Wire a,b,ci,sum,co;Assign co,sum=a+b+ci;Endmodulemodule test_for_addbit;reg a, b, ci ;addbit u1(a, b, ci ,sum,

25、 co);initialbegin a = 0; b = 0; ci=0;#10a = 0; b = 0; ci=1;#10a = 0; b = 1; ci=0;#10a = 0; b = 1; ci=1;#10a = 1; b = 0; ci=0;#10a = 1; b = 0; ci=1; #10 a = 1; b = 1; ci=0; #10 a = 1; b = 1; ci=1;#10$finish;endinitial$monitor( $time, “ a=%b b=%b ci=%b sum=%b co=%b”, a,b,ci,sum, co );endmodule3.please

26、 write out verilog code and test bench for 4-1 MUXmodule mux (a,b,c,d,sel,y);input a,b,c,d;input1:0sel;output y;reg y;always (a or b or c or d or sel)case (sel)o: y=a;1:y=b;2: y=c;3: y=d;Default:$display(“error in sel);EndcaseEndmodulemodule test_for_mux;reg a,b,c,d,sel;/ 調(diào)用DUTmux u1(a,b,c,d,sel,y);

27、/ 產(chǎn)生測試激勵(lì)信號(hào)initialbegin a = 0; b = 1; c=0;d=0;sel = 01;#10a = 1;b=0;sel=00;#10c = 1;a=0; sel=10;#10c=0;d=1;sel=11;#10a = 1;b=0;sel=01;#10c = 1;a=0; sel=11;#10$finish;end/ 檢測輸出信號(hào)initial$monitor( $time, “ a=%b b=%b c=%b sel=%b y=%b”, a,b,c,d,sel,y );endmodule4 please write out verilog code and test ben

28、ch for a 4 bit half adder Module adder (a,b,sum,carry) Input3:0 a,b; Output3:0sum; Output carry; Reg3:0 sum; Reg carry; Always ( a or b) Begin carry, sum=a+b; End Endmodulemodule test_for_adder;reg3:0 a, b;/ 調(diào)用DUTadder u1(a,b,sum,carry);/ 產(chǎn)生測試激勵(lì)信號(hào)initialbegin a = 4b0000; b = 4b0001; #10a = 4b0001; b

29、 = 4b1001;#10a = 4b0010; b = 4b0101; #10a = 4b0100; b = 4b1001; #10a = 4b1000; b = 4b1101; #10a = 4b1001; b = 4b1111; #10 a = 4b1100; b = 4b1010; #10 a = 4b1101; b = 4b0011;#10$finish;end/ 檢測輸出信號(hào)initial$monitor( $time, “ a=%b b=%b sum=%b carry=%b”, a,b, sum, carry);Endmodule鎢賬唐鬃滑搔汪餃曼稚汁摯球奴虹情箕褂遞費(fèi)變吞烽薩帥界禾蹤邵