同步時序狀態(tài)機(jī)(同步時序邏輯電路)

1、Sequential Logic Design Principles7.1 Bistable Elements7.2 Latches and Flip-Flops7.4 Clocked Synchronous State-Machine Analysis7.5 Clocked Synchronous State-Machine DesignReturnIntroduction7.3 Clocked Synchronous State-Machine StructureSequential Logic Design Principles A sequential logic circuit is

2、 one whose outputs depend not only on its current inputs, but also on the past sequence of inputs, possibly arbitrarily far back in time.CombinationalcircuitMemorycircuitZ1ZjY1Yr.X1XiQ1Qr.output equationdrive equationstate equationZ=F1（X，Qn）Y=F2（X，Qn）Qn+1=F3（Y，Qn）NextReturn Finite-state machine: In

3、a digital logic circuit, state variables are binary values. A circuit with n binary state variables has 2n possible states which is always finite, so sequential circuits are sometimes called finite-state machines.Sequential Logic Design Principles State: The state of a sequential circuit is a collec

4、tion of state variables whose values at any one time contain all the information about the past necessary to account for the circuits future behavior.NextBack Duty cycle: The duty cycle is the percentage of time that the clock signal is at its asserted level.Sequential Logic Design Principles The st

5、ate changes of most sequential circuits occur at times specified by a free-running clock signal.tHtLtperPeriod=tperFrequency=1/tperDuty cycle=tH/tperReturnFF=Flip-Flop 觸發(fā)器CLK=Clock 時鐘Clocked Synchronous State-Machine 同步時序狀態(tài)機(jī)（同步時序邏輯電路）duty cycle 占空比stable 穩(wěn)態(tài)metastable 亞穩(wěn)態(tài)latch 鎖存器master-slave 主從positive-edge-triggered 上升沿觸發(fā)negative-edge-triggered 下降沿觸發(fā)Specialized WordsReturnP