keil調(diào)試環(huán)境下S3C2440s的分析

1、;StandarddefinitionsofModebitsandInterrupt(I&F)flagsinPSRs;向量中斷模式/非向量中斷模式設置;通過PSRs(程序狀態(tài)寄存器)來設置;系統(tǒng)工作模式設定;CPS既當系統(tǒng)前程序狀態(tài)寄存器，SPS福備份程序狀態(tài)寄存器。其中CPS商用一個物理寄存器，而SPSFH共有5個物理寄存器;CPSR寄存器設定：CPSR4.0為M4-M0,通過它可以設定處理器的工作模式Mode_USREQU0x10;用戶模式Mode_FIQEQU0x11;快速中斷模式Mode_IRQEQU0x12;外部中斷模式Mode_SVCEQU0x13;超級用戶模式Mode_ABTEQ

2、U0x17;數(shù)據(jù)訪問終止模式Mode_UNDEQU0x1B;未定義指令終止模式Mode_SYSEQU0x1F;系統(tǒng)模式I_BitEQU0x80;whenIbitisset,IRQisdisabled外部中斷屏蔽位，置1,關閉中斷，置0,打開中斷F_BitEQU0x40;whenFbitisset,FIQisdisabled快速中斷屏蔽位，置1,關閉中斷，置0,打開中斷;StackandHeapDefinitions;/StackConfiguration(StackSizesinBytes);/UndefinedMode;/SupervisorMode;/AbortMode;/FastInte

3、rruptMode;/User/SystemMode;/;棧配置，系統(tǒng)的?？臻g設定UND_Stack_SizeEQU0x00000000;未定義模式的棧大小SVC_Stack_SizeEQU0x00000008;超級用戶模式的棧大小ABT_Stack_SizeEQU0x00000000;數(shù)據(jù)訪問終止模式的棧大小FIQ_Stack_SizeEQU0x00000000;快速中斷模式的棧大小IRQ_Stack_SizeEQU0x00000080;外部中斷模式的棧大小USR_Stack_SizeEQU0x00000400;用戶模式的棧大小ISR_Stack_SizeEQU(UND_Stack_Size

4、+SVC_Stack_Size+ABT_Stack_Size+FIQ_Stack_Size+IRQ_Stack_Size)所有模式的堆棧相加得到總堆棧的大小;ARM的匯編程序由段組成，段是相對獨立的指令或數(shù)據(jù)單位，每個段由AREA偽指令定義，并定義段的屬性。-READWRITE（讀寫）、READONLY（只讀）AREASTACK,NOINIT,READWRITE,ALIGN=3;辟一個堆棧段，段名字為STACK定義為可讀可寫,;不初始化內(nèi)存單元，或?qū)?nèi)存單元初始化為0Stack_MemSPACEUSR_Stack_Size;_initial_spSPACEISR_Stack_Size;匯編代碼

5、的地址標號Stack_Top;堆棧段內(nèi)容結束，在這里放個標號，用來獲得堆棧頂部地址;/HeapConfiguration;/HeapSize（inBytes）AREAHEARNOINIT,READWRITE,ALIGN=3開辟一個段，名字為HEAP可讀可寫，不初始化內(nèi)存單元，或者初始化為0_heap_baseHeap_MemSPACEHeap_Size_heap_limit;MemoryDefinitions;InternalMemoryBaseAddresses;片上SRAM的基地址，即內(nèi)存基地址IRAM_BASEEQU0x40000000;-WatchdogTimerDefinitions

6、WT_BASEEQU0x53000000;WatchdogTimerBaseAddress看門狗te時命基地址WTCON_OFS相對十基址EQU0x00;WatchdogTimerControlRegisterOffset看門狗控制寄存器偏移地址，WTDAT_OFS相對十基址EQU0x04;WatchdogTimerDataRegisterOffset看門狗數(shù)據(jù)寄存命偏移地址,WTCNT_OFS址，相對十基址EQU0x08;WatchdogTimerCountRegisterOffset看門狗計數(shù)寄存器偏移地;/WatchdogTimerSetup;/WatchdogTimerControlR

7、egister(WTCON);/PrescalerValue;/WatchdogTimerEnable;/ClockDivisionFactor;/163264128;/ResetEnable;/;/WatchdogTimerDataRegister(WTDAT);/CountReloadValue;/;/WatchdogTimerSetupWT_SETUPEQU1;看門狗設置WTCON_ValEQU0x00000000;看門狗控制寄存器設置，關閉看門狗WTDAT_ValEQU0x00008000;看門狗數(shù)據(jù)寄存器設置，初始值即為0x8000;ClockandPowerManagementDe

8、finitionsCLOCK_BASEEQU0x4C000000;ClockBaseAddress;時鐘基地址LOCKTIME_OFSEQU0x00;PLLLockTimeCountRegisterOffset;鎖相環(huán)鎖定時間計數(shù)寄存器偏移地址，相對于基址MPLLCON_OFSEQU0x04;MPLLConfigurationRegisterOffset;MPLL配置寄存器偏移地址，相對于基址，主時鐘源PLLUPLLCON_OFSEQU對十基址，USB時鐘源PLL0x08;UPLLConfigurationRegisterOffset;UPLL配置寄存器偏移地址，相CLKCON_OFS對十基址

9、EQU0x0C;ClockGeneratorControlRegOffset;時鐘控制寄存器偏移地址，相CLKSLOW_OFS址，相對十基址EQU0x10;ClockSlowControlRegisterOffset;時鐘減慢控制寄存器偏移地CLKDIVN_OFS相對十基址EQU0x14;ClockDividerControlRegisterOffset;時鐘分頻器控制寄存器偏移地址，CAMDIVN_OFSEQU器偏移地址，相對于基址，0x18UPLL提供;CameraClockDividerRegisterOffset;攝像頭時鐘分頻器控制寄存;/ClockSetup;/PLLLockTim

10、eCountRegister(LOCKTIME);/U_LTIME:UPLLLockTimeCountValueforUCLK;/M_LTIME:MPLLLockTimeCountValueforFCLK,HCLKandPCLK;/;/MPLLConfigurationRegister(MPLLCON);/MPLL=(2*m*Fin)/(p*2As);/m:MainDividermValue;/m=MDIV+8;/p:Pre-dividerpValue;/p=PDIV+2;/s:PostDividersValue;/s=SDIV;/;/UPLLConfigurationRegister(UPL

11、LCON);/UPLL=(m*Fin)/(p*2As);/m:MainDividermValue;/m=MDIV+8;/p:Pre-dividerpValue;/p=PDIV+2;/s:PostDividersValue;/s=SDIV;/AC97Enable;/CameraEnable;/SPIEnable;/IISEnable;/IICEnable;/ADC+TouchScreenEnable;/RTCEnable;/GPIOEnable;/UART2Enable;/UART1Enable;/UART0Enable;/SDIEnable;/PWMTIMEREnable;/USBDevice

12、Enable;/USBHostEnable;/LCDCEnable;/NANDFLASHControllerEnable;/SLEEPEnable;/IDLEBITEnable;/;/ClockSlowControlRegister(CLKSLOW);/UCLK_ON:UCLKON;/MPLL_OFF:TurnoffPLL;/SLOW_BIT:SlowModeEnable;/SLOW_VAL:SlowClockDivider;/;/ClockDividerControlRegister(CLKDIVN);/DIVN_UPLL:UCLKSelect;/UCLK=UPLLclock;/UCLK=U

13、PLLclock/2;/HDIVN:HCLKSelect;/HCLK=FCLK;/HCLK=FCLK/2;/HCLK=FCLK/4ifHCLK4_HALF=0inCAMDIVN,elseHCLK=FCLK/8;/HCLK=FCLK/3ifHCLK3_HALF=0inCAMDIVN,elseHCLK=FCLK/6;/PDIVN:PCLKSelect;/PCLK=HCLK;/PCLK=HCLK/2;/;/CameraClockDividerControlRegister(CAMDIVN);/DVS_EN:ARMCoreClockSelect;/ARMcorerunsatFCLK;/ARMcorer

14、unsatHCLK;/HCLK4_HALF:HDIVNDivisionRateChangeBit;/IfHDIVN=2inCLKDIVNthenHCLK=FCLK/4;/IfHDIVN=2inCLKDIVNthenHCLK=FCLK/8;/HCLK3_HALF:HDIVNDivisionRateChangeBit;/IfHDIVN=3inCLKDIVNthenHCLK=FCLK/3;/IfHDIVN=3inCLKDIVNthenHCLK=FCLK/6;/CAMCLKSelect;/CAMCLK=UPLL;/CAMCLK=UPLL/CAMCLK_DIV;/CAMCLK_DIV:CAMCLKDiv

15、ider;/CameraClock=UPLL/(2*(CAMCLK_DIV+1);/DividerisusedonlyifCAMCLK_SEL=1;/;/ClockSetupCLOCK_SETUPEQU0;時鐘設置LOCKTIME_ValEQU0X0FFF0FFF;PLLt定時間計數(shù)器值MPLLCON_ValEQU0x00043011;MPLL配置寄存器值UPLLCON_ValEQU0x00038021;UPLL配置寄存器值CLKCON_ValEQU0X001FFFF0;時鐘配置寄存器值CLKSLOW_ValEQU0x00000004;時鐘減慢控制寄存器值CLKDIVN_ValEQU0X000

16、0000F;時鐘分頻控制寄存器值CAMDIVNValEQU0x00000000;攝像頭分頻控制寄存器值MemoryControllerDefinitions;存儲控制器設置MC_BASEEQU0x48000000;MemoryControllerBaseAddress;存儲控制器基地址BWSCON_OFSEQU0x00;BusWidthandWaitStatusCtrlOffset;總線寬度和等待控制寄存器BANKCON0_OFSEQU0x04;Bank0ControlRegisterOffset;BANK0-BOOTROM控制寄存器設置BANKCON1_OFSEQU0x08;Bank1Con

17、trolRegisterOffset;BANK1BANKCON2_OFSEQU0x0C;Bank2ControlRegisterOffset;BANK2BANKCON3_OFSEQU0x10;Bank3ControlRegisterOffset;BANK3BANKCON4_OFSEQU0x14;Bank4ControlRegisterOffset;BANK4BANKCON5_OFSEQU0x18;Bank5ControlRegisterOffset;BANK5BANKCON6_OFSEQU0x1C;Bank6ControlRegisterOffset;BANK6BANKCON7_OFSEQU0

18、x20;Bank7ControlRegisterOffset;BANK7REFRESH_OFSEQU0x24;SDRAMRefreshControlRegisterOffset;DRAM/SDRAM刷新控制BANKSIZE_OFSEQU0x28;FlexibleBankSizeRegisterOffset;可調(diào)的bank大小寄存器MRSRB6_OFSEQU0x2C;Bank6ModeRegisterOffset;模式控制寄存器bank6MRSRB7_OFSEQU0x30;Bank7ModeRegisterOffset;模式控制寄存器bank7;/MemoryControllerSetup;/B

19、usWidthandWaitControlRegister(BWSCON);/ST7:UseUB/LBforBank7;/WS7:EnableWaitStatusforBank7;/ST6:UseUB/LBforBank6;/WS6:EnableWaitStatusforBank6;/DW6:DataBusWidthforBank6;/8-bit16-bit32-bitReserved;/ST5:UseUB/LBforBank5;/WS5:EnableWaitStatusforBank5;/DW5:DataBusWidthforBank5;/8-bit16-bit32-bitReserved;

20、/ST4:UseUB/LBforBank4;/WS4:EnableWaitStatusforBank4;/DW4:DataBusWidthforBank4;/8-bit16-bit32-bitReserved;/ST3:UseUB/LBforBank3;/WS3:EnableWaitStatusforBank3;/DW3:DataBusWidthforBank3;/8-bit16-bit32-bitReserved;/ST2:UseUB/LBforBank2;/WS2:EnableWaitStatusforBank2;/DW2:DataBusWidthforBank2;/8-bit16-bit

21、32-bitReserved;/WS1:EnableWaitStatusforBank1;/DW1:DataBusWidthforBank1;/8-bit16-bit32-bitReserved;/DW0:IndicateDataBusWidthforBank0;/16-bit32-bit;/;/Bank0ControlRegister(BANKCON0);/Tacs:AddressSet-upTimebeforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2c

22、locks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:ChipSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2clocks4clocks;/Tacp:PageModeAccessCycleatPageMode;/2clocks3clocks4clocks6clocks;/PMC:PageModeC

23、onfiguration;/normal(1data)4data8data16data;/;/Bank1ControlRegister(BANKCON1);/Tacs:AddressSet-upTimebeforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2clocks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:Chi

24、pSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2clocks4clocks;/Tacp:PageModeAccessCycleatPageMode;/2clocks3clocks4clocks6clocks;/PMC:PageModeConfiguration;/normal(1data)4data8data16data;/;/Bank2ControlRegister(BANKCON2);/Tacs:AddressSet-upTimeb

25、eforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2clocks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:ChipSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clock

26、s2clocks4clocks;/Tacp:PageModeAccessCycleatPageMode;/2clocks3clocks4clocks6clocks;/PMC:PageModeConfiguration;/normal(1data)4data8data16data;/;/Bank3ControlRegister(BANKCON3);/Tacs:AddressSet-upTimebeforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2clocks4

27、clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:ChipSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2clocks4clocks;/Tacp:PageModeAccessCycleatPageMode;/2clocks3clocks4clocks6clocks;/PMC:PageModeConfigu

28、ration;/normal(1data)4data8data16data;/;/Bank4ControlRegister(BANKCON4);/Tacs:AddressSet-upTimebeforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2clocks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:ChipSelec

29、tionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2clocks4clocks;/Tacp:PageModeAccessCycleatPageMode;/2clocks3clocks4clocks6clocks;/PMC:PageModeConfiguration;/normal(1data)4data8data16data;/;/Bank5ControlRegister(BANKCON5);/Tacs:AddressSet-upTimebeforen

30、GCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2clocks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:ChipSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2cloc

31、ks4clocks;/Tacp:PageModeAccessCycleatPageMode;/2clocks3clocks4clocks6clocks;/PMC:PageModeConfiguration;/normal(1data)4data8data16data;/;/Bank6ControlRegister(BANKCON6);/MemoryTypeSelection;/ROMorSRAMSDRAM;/Tacs:AddressSet-upTimebeforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebe

32、forenOE;/0clocks1clocks2clocks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:ChipSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2clocks4clocks;/Tacp/Trcd:PageModeAccessCycleatPageMode/RAStoCASDelay;

33、/ParameterdependsonMemoryType:iftypeSRAMthenparameterisTacp,;/iftypeisSDRAMthenparameterisTrcd;/ForSDRAM6cyclessettingisnotallowed;/2clocks3clocks4clocks6clocks;/PMC/SCAN:PageModeConfiguration/ColumnAddressNumber;/ParameterdependsonMemoryType:iftypeSRAMthenparameterisPMC,;/iftypeisSDRAMthenparameter

34、isSCAN;/;/Bank7ControlRegister(BANKCON7);/MemoryTypeSelection;/ROMorSRAMSDRAM;/Tacs:AddressSet-upTimebeforenGCS;/0clocks1clocks2clocks4clocks;/Tcos:ChipSelectionSet-upTimebeforenOE;/0clocks1clocks2clocks4clocks;/Tacc:AccessCycle;/1clocks2clocks3clocks4clocks;/6clocks8clocks10clocks14clocks;/Tcoh:Chi

35、pSelectionHoldTimeafternOE;/0clocks1clocks2clocks4clocks;/Tcah:AddressHoldTimeafternGCS;/0clocks1clocks2clocks4clocks;/Tacp/Trcd:PageModeAccessCycleatPageMode/RAStoCASDelay;/ParameterdependsonMemoryType:iftypeSRAMthenparameterisTacp,;/iftypeisSDRAMthenparameterisTrcd;/ForSDRAM6cyclessettingisnotallo

36、wed;/2clocks3clocks4clocks6clocks;/PMC/SCAN:PageModeConfiguration/ColumnAddressNumber;/ParameterdependsonMemoryType:iftypeSRAMthenparameterisPMC,;/iftypeisSDRAMthenparameterisSCAN;/SDRAMRefreshControlRegister(REFRESH);/REFEN:SDRAMRefreshEnable;/TREFMD:SDRAMRefreshMode;/CBR/AutoRefreshSelfRefresh;/Tr

37、p:SDRAMRASPre-chargeTime;/2clocks3clocks4clocksReserved;/Tsrc:SDRAMSemiRowCycleTime;/SDRAMRowcycletime:Trc=Tsrc+Trp;/4clocks5clocks6clocks7clocks;/RefreshCounter;/RefreshPeriod=(2048-RefreshCount+1)/HCLK;/;/FlexibleBankSizeRegister(BANKSIZE);/BURST_EN:ARMCoreBurstOperationEnable;/SCKE_EN:SDRAMPowerD

38、ownModeEnable;/SCLK_EN:SCLKEnabledDuringSDRAMAccessCycle;/SCLKisalwaysactiveSCLKisactiveonlyduringtheaccess;/BK76MAP:BANK6andBANK7MemoryMap;/32MB/32MB64MB/64MB128MB/128MB;/2MB/2MB4MB/4MB8MB/8MB16MB/16MB;/RefreshCounter;/RefreshPeriod=(2048-RefreshCount+1)/HCLK;/;/SDRAMModeRegisterSetRegister6(MRSRB6

39、);/WBL:WriteBurstLength;/Burst(Fixed);/TM:TestMode;/Moderegisterset(Fixed);/CL:CASLatency;/1clocks2clocks3clocks;/BT:BurstType;/Sequential(Fixed);/BL:BurstLength;/1(Fixed);/;/SDRAMModeRegisterSetRegister7(MRSRB7);/WBL:WriteBurstLength;/Burst(Fixed);/TM:TestMode;/Moderegisterset(Fixed);/CL:CASLatency

40、;/1clocks2clocks3clocks;/BT:BurstType;/Sequential(Fixed);/1(Fixed);/;/MemoryControllerSetupMC_SETUPEQU0;存儲器控制寄存器設置BWSCON_ValEQU0x22000000BANKCON0_ValEQU0x00000700BANKCON1_ValEQU0x00000700BANKCON2_ValEQU0x00000700BANKCON3_ValEQU0x00000700BANKCON4_ValEQU0x00000700BANKCON5_ValEQU0x00000700BANKCON6_ValE

41、QU0x00018005BANKCON7_ValEQU0x00018005REFRESH_ValEQU0x008404F3BANKSIZE_ValEQU0x00000032MRSRB6_ValEQU0x00000020MRSRB7_ValEQU0x00000020;I/OPortDefinitions;GPI。設置GPA_BASEEQU0x56000000;GPABaseAddressGPB_BASEEQU0x56000010;GPBBaseAddressGPC_BASEEQU0x56000020;GPCBaseAddressGPD_BASEEQU0x56000030;GPDBaseAddre

42、ssGPE_BASEEQU0x56000040;GPEBaseAddressGPF_BASEEQU0x56000050;GPFBaseAddressGPG_BASEEQU0x56000060;GPGBaseAddressGPH_BASEEQU0x56000070;GPHBaseAddressGPJ_BASEEQU0x560000D0;GPJBaseAddressGPCON_OFSEQU0x00;ControlRegisterOffsetGPDAT_OFSEQU0x04;DataRegisterOffsetGPUP_OFSEQU0x08;Pull-upDisableRegisterOffset;/I/OSetupGP_SETUPEQU1;/PortASettings;/PortAControlRegister(GPACON);/GPA22OutputnFCE;/GPA21OutputnRSTOUT;/GPA20OutputnFRE;/GPA19Out