模擬集成電路設(shè)計(jì)第一章-綜述

1、Introduction of this courseLecturer: Dr. Wu Zhaohui,School of Electronic and Information Engineering , SCUT , ,ourse Name: Analysis and Design of Analog Integrated CircuitsIntroduction of this courseText book(英文版教材）英文版教材）: 1、Behzad Razavi, 模擬CMOS集成電路設(shè)計(jì)（影印版），清華大學(xué)出版社， 2005。中文翻譯教材中文翻譯教材: :

2、 1、模擬CMOS集成電路設(shè)計(jì) 作者：畢查德拉扎維，譯：陳貴燦、程軍、 張瑞智出版社：西安交通大學(xué)出版社 ，2003。Main reference book（參考書）（參考書）: 1、CMOS模擬集成電路設(shè)計(jì)（第二版）作者：phillip E. Allen, Douglas R. Holberg譯：馮軍、李智群出版社：電子工業(yè)出版社，2005。Introduction to Analog DesignWhy analog? (1)1. Processing of Natural SignalsNatural signals are analog, while many signals we u

3、sed are digitalSo we need ADC to convert an analog signal to digital signal and then use DSP to process the digital signal.Fig. 1.1a Digitization of a natural signalsIntroduction to Analog DesignWhy analog? (2)1. Processing of Natural SignalsWell some times, the natural signals are very small, or th

4、ere exist many interferers (干擾）. In this case, the small signal cannot be converted directly into digital correctly. Therefore, an amplifier (放大器）and a filter (濾波器）are needed before converting.Fig. 1.1b Addition of amplification and filtering for higher sensitivity (靈敏度）Introduction to Analog Design

5、Why analog? (3)2. Digital communicationsA digital signal through a long cable will be attentuated and distorted.Multi-level signal processing maybe needed to reduce the required transmission bandwidth (傳輸帶寬）Need a DAC in the transmitter to produce multiple levels from the grouped binary data and an

6、ADC in the receiver to determine which level has been transmitted.Fig. 1.2 Attentuation（衰減） and Distortion （失真） of data through a lossy cableIntroduction to Analog DesignWhy analog? (4)Fig. 1.3 Multi-level signaling to reduce the bandwidthIntroduction to Analog DesignWhy analog? (5)3. Disk Drive Ele

7、ctronics The signal received from the magnetic head is really weak and the noise is quite high.Just like Fig. 1.1b, there needs amplification, filtering and ADC for further processing.Fig. 1.4 Data stored in and received from a hard diskIntroduction to Analog DesignWhy analog? (6)3. Wireless Receive

8、rs A radio-frequency (RF,射頻) signal received by a cell phone （手機(jī)）is usually only a few microvolts and its center frequency is usually 1Ghz or higher, while the value of the interferers are higher.Therefore, a high frequency of amplifier and filter are needed.Fig. 1.5 Signal and interferers received

9、by the antenna of a wireless receiver.Introduction to Analog DesignWhy analog? (7)4. Optical Receivers High frequency signals are not suitable for transmitting over long distance in the traditional cable due to the severe interference and considerable attenuation because of the limited bandwidth of

10、the cable.In this case, the electrical high frequency signals are converted into the optical signals first by the laser diode, then these optic signals are transmitted by an optical fiber, which has extremely wide band and very low loss.In the other end, the optical signals are converted into electr

11、ical signals again by the photodiode.Introduction to Analog DesignWhy analog? (8)Since the electrical current converted by a photodiode is very small, the receiver after the photodiode must process a low-level signal at a very high speed, which requires a low noise, broadband circuit design. Fig. 1.

12、6 Optical fiber systemIntroduction to Analog DesignWhy analog? (9)5. Smart sensors When the car hits an obstacle, the drop in the speed is measured as acceleration. If this acceleration exceeds a certain threshold, the air bag will be released.Since the change of the capacitance is quite small, the

13、electrical signal received is very weak and the there exist large interference, hence the amplification, filtering and ADC are needed to handle these small signals properly.Fig. 1.7 Differential accelerometer used in the ABS (安全氣囊） system of a car.Introduction to Analog DesignWhy CMOS (1)?CMOS is wi

14、dely used in digital circuit design due to its low power and low fabrication cost.In the old age, bipolar is often used in the analog circuit design because the speed of the CMOS is not high enough.After scaling down again and again, the speed of CMOS is greatly increased. Nowadays, it is comparable

15、 with BIP. Introduction to Analog DesignWhy CMOS (2)?Combining with other advantages, it is time for CMOS to replace bipolar in the analog IC design.The most important force to apply CMOS technology to analog design is the possibility of placing both analog and digital circuits on the same chip so a

16、s to improve the overall performance and reduce the cost of packaging.This is often called as mixed IC design, which is very hot in IC design nowadays.Introduction to Analog DesignLevel of abstractionFig. 1.8 Abstraction levels in circuit design數(shù)?；旌螴C設(shè)計(jì)實(shí)例（1）采用硅微機(jī)械加工技術(shù)的植入式記錄電極及其在大鼠體內(nèi)的記錄結(jié)果采用硅微機(jī)械加工技術(shù)的植

17、入式記錄電極及其在大鼠體內(nèi)的記錄結(jié)果 植入生物體的微電子電路在臨床上已廣泛應(yīng)用于心率調(diào)節(jié)、人工耳蝸、人工視網(wǎng)膜修復(fù)、泌尿控制與功能性神經(jīng)肌肉電刺激、以及癲癇和脊柱損傷等康復(fù)醫(yī)療中。無線植入式神經(jīng)信號(hào)采集系統(tǒng)神經(jīng)信號(hào)記錄電極2. 體內(nèi)至體外無線數(shù)據(jù)傳送通路1. 體外至體內(nèi)的無線能量及控制數(shù)據(jù)傳送通路數(shù)模混合IC設(shè)計(jì)實(shí)例（2）數(shù)?；旌螴C設(shè)計(jì)實(shí)例（3）新型新型8通道低噪聲神經(jīng)信號(hào)前端放大芯片通道低噪聲神經(jīng)信號(hào)前端放大芯片8通道前端芯片關(guān)鍵指標(biāo)工藝0.35m CMOS process帶內(nèi)等效輸入噪聲2.602 Vrms 總面積1700m2479m通道增益46.38dB 5kHz電源5V低頻截止點(diǎn)8.

18、2 Hz功耗/CH39.79uA/CH高頻截止點(diǎn)10.71K HzTHD(1%)8.1mV共模抑制比70 dB8通道前端芯片版圖數(shù)?；旌螴C設(shè)計(jì)實(shí)例（4）低功耗低功耗12位差分位差分SAR A/DADC電路框圖ADC芯片照片ADC芯片關(guān)鍵指標(biāo)工藝0.35m CMOS process信噪失真比58.3dB 1.253kHz分辨率12bit無雜散動(dòng)態(tài)范圍72.6dB 1.253kHz采樣速度20KS/s有效位9.4bits電源3.3V微分非線性2.2LSB輸入幅度2Vpp differential積分非線性2.5LSB數(shù)?；旌螴C設(shè)計(jì)實(shí)例（5） 433M Class E 功率放大器功率放大器433

19、M Class E 功率放大器版圖主要參數(shù)主要參數(shù)結(jié)果結(jié)果工藝最小尺寸/VDD0.18um/1.8V芯片面積(mm2)1.4*1.4功耗(mW)12S11（dB）-11S22（dB）-15功率增益（dB）11.8附加功率效率（PAE）38%數(shù)?；旌螴C設(shè)計(jì)實(shí)例（6） 433M AM Transmitter 主要參數(shù)主要參數(shù)測試結(jié)果測試結(jié)果工藝最小尺寸/VDD0.18m /1.8V芯片總面積(mm2)0.25載波頻率(MHz)433.92功耗(mW)15輸出信號(hào)包絡(luò)310mVpp*調(diào)制深度52%*表3 433.92MHz AM發(fā)射芯片關(guān)鍵性能指標(biāo)433M AM Transmitter 版圖433

20、M AM Transmitter output waveform數(shù)?；旌螴C設(shè)計(jì)實(shí)例（7） 433M LNA 表3 433.92MHz AM發(fā)射芯片關(guān)鍵性能指標(biāo)參數(shù)參數(shù)測試結(jié)果測試結(jié)果工藝最小尺寸/VDD0.18m/1.8V功率增益（dB）16.8功耗(mW)81dB壓縮點(diǎn)（dB）-30噪聲系數(shù)（dB）3.13433M LNA 版圖433M LNA Noise FactorMaterials provided in this Lecture (1)(1) Introduction(2) Basic MOS Device Physics （基本MOS器件物理）(3) Single-Stage Amplifiers (單級(jí)放大器）(4) Differential Amplifiers （差分放大器）(5)