成果ni官方培訓(xùn)lesson multirate diagram and fpga

1、Describe how to use the multirate dataflow interface to iterate algorithm design before migrating your application to the FPGA and host.1Using Multirate DiagramsConverting Floating-Point to Fixed-PointIntegrating Multirate Diagrams with FPGA VIsLesson 6Multirate Diagram and FPGAA. Using Multirate Di

2、agramsExplain the differences between multirate diagram and G.Multirate DiagramEnvironment DifferencesMultirate Dataflow Behavior2Comparing G and Multirate DataflowStructures and canvas impose ordering.Dataflow actors can fire simultaneously, and dataflow controls execution.A. Using Multirate Diagra

3、msABCDMultirate Diagram DataflowABCDG Structured DataflowACABCBGMRDG and MRD ExecutionA. Using Multirate DiagramsG Needs Loops to Mimic Multirate Diagram BehaviorMultirate diagram:G implementation:A. Using Multirate DiagramsImplementing Multirate in GA. Using Multirate DiagramsMultirate Diagram Unde

4、r the HoodSample Counts & Buffer Sizes:Schedule:A. Using Multirate DiagramsAccess the multimedia module through the software:LearnProgramming FPGAIntroduction to Multirate Dataflow8Introduction to Multirate DataflowQuickly Iterate Algorithm Prototyping in MRDA. Using Multirate DiagramsIdeal start fo

5、r algorithm prototypingSignal processing IP stitchingMultirate DiagramDataflow (G) algorithm designTransition designs from host to FPGAFPGA IPClock Driven LogicMapping &OptimizationFPGADifferences between G and MRD Editors 10A. Using Multirate DiagramsA. Integrating MRD with FPGA VINo PanelDifferent

6、 PalettesGMultirate Diagram11Use a multirate diagram to create a 5 MHz CP OFDM modulator with the same functionality as the OFDM in previous exercises.Exercise 6-1Build an OFDM Transmitter Using Multirate DiagramExercise 6-112Build an OFDM Transmitter Using Multirate DiagramB. Converting Floating Po

7、int to Fixed PointConvert a floating-point OFDM transmitter to a fixed-point OFDM transmitter.Floating Point on the FPGAB. Converting Floating Point to Fixed PointCan be costly in terms of FPGA resources and power consumption.Not supported or processed inefficiently on some FPGAs.Fixed-Point Numbers

8、 Enable fast and efficient FPGA implementation. Have size and speed advantages of integer math. Simplify computations. Are limited in the range of numbers. Have a maximum size of 64 bits. Are susceptible to problems of overflow.B. Converting Floating Point to Fixed PointAbundant FPGA = Highest Preci

9、sionLess Resources = Careful ConsiderationIP Availability and CapabilityFloat-to-Fixed ConversionRequired effort depends on application and FPGA resources:B. Converting Floating Point to Fixed PointAccess the multimedia module through the software:LearnProgramming FPGAIntroduction to Float-to-Fixed

10、Conversion17Introduction to Float-to-Fixed Conversion Float to Fixed-Point ConversionObserve the effects of exceeding the lower bound of a fixed-point data range.B. Converting Floating Point to Fixed PointFPGA Code Development, Simulation and VerificationWrite FPGA CodeSimulate on PCWrite Host CodeS

11、imulate using emulation modeCompile FPGA VIB. Converting Floating Point to Fixed PointFixed-Point Data TypesFixed-point is a collection of data types with different ranges of values.Range is defined by minimum value, maximum value, and deltaRange of values and resolution are dependent upon three fac

12、tors.Sign EncodingBits to the left of the decimal pointBits to the right of the decimal pointB. Converting Floating Point to Fixed PointFixed-Point ConfigurationB. Converting Floating Point to Fixed PointNumeric Representation ExamplesB. Converting Floating Point to Fixed PointRepresentation deltaMi

13、n ValueMax ValueU810255I81-128127U8 0.50127.5U8 0.25063.75I8 0.5-6463.5I8 0.25-3231.75U8 0.003900.9961Fixed-Point ArithmeticLargest input values modated (up to 64 bits)Propagates range of values along each wireCalculated to be as small as possible without losing dataB. Converting Floating Point to F

14、ixed PointFloating Point/Fixed Point Summary24Floating PointLarger accuracyEasier to programAccess larger memoryFixed PointCheaperSmallerLess power consumingHarder to programB. Converting Floating Point to Fixed Point25Use the float-to-fixed-point conversion utility to convert floating-point data an

15、d arithmetic to fixed-point for FPGA deployment and build a testbench to test the success of the conversion.Exercise 6-2Convert Floating-Point Design to Fixed-PointExercise 6-226Convert Floating-Point Design to Fixed-PointC. Integrating Multirate Diagrams with FPGA VIsExplain how to pass information

16、 between multirate diagrams and an FPGA VI.27Data Ports Relay Data to/from MRDs 28Data ports are similar to controls and indicators in a VI.Data ports are called input and output ports.C. Integrating Multirate Diagrams with FPGA VIsCalling a Multirate Diagram from the Host29C. Integrating Multirate

17、Diagrams with FPGA VIsCalling a Multirate Diagram from an FPGA VI30C. Integrating Multirate Diagrams with FPGA VIsCalling an MRD from a VI31C. Integrating Multirate Diagrams with FPGA VIsConstraints on I/O ports, views, pipelining, and feedback from the compiler.32Multirate Diagram and FPGA VI 33Int

18、egrate fixed-point OFDM transmitter on FPGA. Configure the build specification and initiate the compile.Exercise 6-3Integrate the OFDM Transmitter MRD into an FPGA VIExercise 6-334Integrate the OFDM Transmitter MRD into an FPGA VI35Update the full-duplex streaming VI to interface with code running on the FPGA in the USRP. Exercise 6-4Set Up Communication between the Host and FPGAExercise 6-436Set Up Communication between the Host and FPGAActivity37Lesson ReviewFor each feature, specify whether it applies to multirate diagram (MRD), G diagram, or both.38Fl