設(shè)計(jì)示例2寄存器堆設(shè)計(jì)

1、設(shè)計(jì)示例2：寄存器堆設(shè)計(jì)功能概述：MIPS指令格式中的寄存器號(hào)是5bits，指令可以訪問(wèn)25=32個(gè)32位的寄存器。這樣的一堆寄存器“堆在一起”構(gòu)成一個(gè)寄存器堆（Register File）。模塊框圖如圖1所示：圖1 模塊框圖結(jié)構(gòu)框圖：接口說(shuō)明：表1： 寄存器堆模塊接口信號(hào)說(shuō)明表序號(hào)接口信號(hào)名稱(chēng)方向說(shuō)明備注ClkI處理器工作時(shí)鐘，頻率為50MhzRst_nI復(fù)位信號(hào)，低有效Raddr14:0I讀寄存器堆時(shí)的第1個(gè)寄存器下標(biāo)Raddr24:0I讀寄存器堆時(shí)的第2個(gè)寄存器下標(biāo)Waddr4:0I寫(xiě)寄存器堆時(shí)的寄存器下標(biāo)WeI寄存器堆寫(xiě)使能Wdata 31:0I待寫(xiě)入寄存器堆的數(shù)據(jù)Rdata 131:

2、0O讀寄存器堆時(shí)第1個(gè)寄存器的輸出Rdata 231:0O讀寄存器堆時(shí)第2個(gè)寄存器的輸出Vcc電源Gnd地線圖2 寄存器堆寫(xiě)時(shí)序框圖設(shè)計(jì)電路源代碼/功能描述風(fēng)格寄存器堆的設(shè)計(jì)module regfile(inputclk,input rst_n,/寫(xiě)端口input we, /寫(xiě)使能input4:0 waddr, /寫(xiě)寄存器下標(biāo)input31:0wdata, /待寫(xiě)入寄存器堆的數(shù)據(jù)/讀端口1input4:0raddr1, /讀端口1寄存器下標(biāo)output31:0 rdata1,/從端口1讀出的寄存器堆的數(shù)據(jù)/讀端口2input4:0raddr2, /讀端口2寄存器下標(biāo)output31:0 rda

3、ta2 /從端口2讀出的寄存器堆的數(shù)據(jù));reg31:0 regs0:31; /32個(gè)32位寄存器堆/Write operationalways (posedge clk or negedge rst_n) begin if(!rst_n) begin:reset_all_registers /將32個(gè)寄存器復(fù)位為0. integer i;for(i=0;i32;i=i+1) regsi = 32d0; end else begin /寫(xiě)寄存器堆有效時(shí)，更新寄存器堆中某個(gè)寄存器的數(shù)據(jù)if(we = 1b1) & (waddr != 5h0) begin regswaddr = wdata; e

4、nd endend/Read port1 operation assign rdata1 = (raddr1 = 5d0) ? 32d0 : regsraddr1;/Read port2 operation assign rdata2 = (raddr2 = 5d0) ? 32d0 : regsraddr2;endmodule/風(fēng)格2module regfile2(inputclk,input rst_n,/寫(xiě)端口input we,input4:0waddr,input31:0wdata,/讀端口1input4:0raddr1,output reg31:0 rdata1,/讀端口2input4

5、:0raddr2,output reg31:0 rdata2);reg31:0 reg0,reg1,reg2,reg3;/Write operationalways (posedge clk) begin if(!rst_n) begin reg0 = 32d0; reg1 = 32d0;reg2 = 32d0;reg3 = 32d0; end else beginif(we = 1b1) begin case(waddr) 5d0: reg0 = wdata;5d1: reg1 = wdata;5d2: reg2 = wdata;5d3: reg3 = wdata; default: ; e

6、ndcase end endend/Read port1 operation always (*) begin case(raddr1) 5d0: rdata1 = 32d0; 5d1: rdata1 = reg1; 5d2: rdata1 = reg2; 5d3: rdata1 = reg3; default: rdata1 = 32d0; endcaseend/Read port2 operation always (*) begin case(raddr2) 5d0: rdata2 = 32d0; 5d1: rdata2 = reg1; 5d2: rdata2 = reg2; 5d3:

7、rdata2 = reg3; default: rdata2 = 32d0; endcaseendendmodule設(shè)計(jì)電路仿真所設(shè)計(jì)的指令存儲(chǔ)器模塊電路，采用Modelsim10.1a仿真器工具進(jìn)行了設(shè)計(jì)仿真驗(yàn)證，驗(yàn)證結(jié)果表明存儲(chǔ)器功能以及接口時(shí)序完全正確，如下是仿真驗(yàn)證的波形圖。附件1是仿真激勵(lì)源代碼。圖5 寄存器堆電路讀寫(xiě)仿真波形圖存在問(wèn)題及解決方式方法，設(shè)計(jì)討論等問(wèn)題討論：/-結(jié)構(gòu)級(jí)與行為級(jí)描述的區(qū)別？ 行為級(jí)建模包括系統(tǒng)級(jí)、算法級(jí)和 HYPERLINK /s?wd=RTL&tn=44039180_cpr&fenlei=mv6quAkxTZn0IZRqIHckPjm4nH00T1d9r

8、HNBrHnLuH-WuHFhP1Rv0ZwV5Hcvrjm3rH6sPfKWUMw85HfYnjn4nH6sgvPsT6KdThsqpZwYTjCEQLGCpyw9Uz4Bmy-bIi4WUvYETgN-TLwGUv3En1mznjbzPHnv t /_blank RTL級(jí)，行為描述以過(guò)程塊為基本組成單位，一個(gè)模塊的行為描述由一個(gè)或多個(gè)并行運(yùn)行的過(guò)程塊組成。結(jié)構(gòu)級(jí)也稱(chēng)為“門(mén)級(jí)和開(kāi)關(guān)級(jí)”，包含模塊實(shí)例和基本元件實(shí)例。XXXXXXXXXYYYYZZZZZZZZZZZ附件1：timescale 1ns/1nsmodule regfile_tb();reg clk;reg rst_n;reg we;

9、reg4:0 waddr,raddr1,raddr2;reg31:0 wdata;wire31:0 rdata1,rdata2;/寄存器模塊實(shí)例化調(diào)用regfile regfile_inst(.clk(clk),.rst_n(rst_n),.we(we),.waddr(waddr),.wdata(wdata),.raddr1(raddr1),.rdata1(rdata1),.raddr2(raddr2),.rdata2(rdata2);/generate the clockinitial beginclk = 1b0;forever #10 clk = clk;endreg5:0 j,k;in

10、itial beginrst_n = 1b0;#20 rst_n = 1b1; / #100 we = 1b1; waddr = 5d5; wdata = $random;#20 waddr = 5d30; wdata = $random;#20 waddr = 5d0; wdata = 32hffff;/#20 raddr1 = 5d5; raddr2 = 5d30;#20 we= 1b0; raddr1 = 5d5; raddr2 = 5d30;#20 raddr1 = 5d0;raddr2 = 5d0;/write all 32 registers #100 we = 1b1; for(j=0;j6d32;j=j+1) begin(posedge clk) #20 waddr = j;