參考-納米時代集成電路

Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines2A

Game

of

Calculation?230.67

=

1?,708,401,590What

does

this

number

mean?Why

do

we

need

to

know

this

number?If

we

say

that

some

industry

grows

with

a

year

to

year

rate

of

2n,

n=year,

is

this

true?The

number

of

transistors

on

a

singlesilicon

chip

doubled

every

18

months.

Ifonly

1

transistor

existed

on

a

chip

in

1965,today

a

single

chip

may

contain

more

than1.7

billion

transistors,

as

(20111965)

×12

÷

18

=30.67.We

are

certainly

shocked

by

this

amazing

law.We

are

curiously

to

know

why

the

law

has

been

valid

for

so

longtime.We

are

also

eagerly

to

know

if

and

how

long

this

law

will

last

inthe

future.3Binary

and

Digital

SystemDecimal<->Binary0<->00001<->00012<->00103<->00114<->01005<->01016<->01107<->01118<->10009<->1001Elements

of

decimal

and

binary

systemDecimal

System:

0,

1,

2,

3,

4,

5,

6,

7,

8,

9Binary

System:

0,

1Real

world

isogA

component

dealing

withdecimal

has

very

high

cost數(shù)模字?jǐn)M世世界界是是虛真擬實的的4Amplifier

and

Binary

CodeAmplifier開到最大：“1”完全關(guān)閉：“0”注：假設(shè)水流時恒定的大壩大壩電勱機發(fā)電機5Vacuum

Tube飛樂266-TH型6電子管3波段收音機陽極6柵極陰極通電后陰極向陽極發(fā)射電子陽極收集電子通過在柵極施加一個電位可以控制仍陰極到陽極通過的電子量要想使陰極能夠發(fā)射電子就要將陰極加熱到數(shù)百攝氏度高溫陰極丌發(fā)射電子時為“0”陰極發(fā)射的電子全部被陽極接收時為“1”ENIAC：

1sectronics

Computer7TransistorW.

Shockley,

J.Bardeen

and

W.

Brattain1947年，第一支晶體管在貝爾實驗室誕生，巴丁、肖兊利和布萊坦獲得1956年物理學(xué)獎8Principle

of

Semiconductor

Transistor柵G源S漏D多晶硅金屬層金屬氧化物半導(dǎo)體晶體管（MOS晶體管）結(jié)構(gòu)圖GSD+

+

+

+

+

+

+

+氧化層

擴散區(qū)硅襯底9Integrated

Circuits1958年，J.

Kilby發(fā)明了集成電路的理論模型1959年，R.Noyce發(fā)明了今天的集成電路PentiumIIIPentiumIV2000年，J.

Kilby獲得物理學(xué)獎10Evolution

of

Computer11Integrated

Circuits

Exist

Everywhere12Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines13IntroductionMoore

&

VonannVonannGolden

MooreScaling-downVon

annArchitectureSemiconductorComputer14Golden

Moore15With

unit

cost

falling

as

thenumber

of

components

percircuit

rise,

by

1975economics

may

dictatesqueezing

as

many

as65,000

components

on

asingle

silicon

chip.Moore’s

Law16Robert

Dennard

and

Dennard’s

Law17Scaling-down等比例縮小的技術(shù)代等比例縮小技術(shù)是年復(fù)一年地將一組(通常多于20個)支配硅器件的技術(shù)參數(shù)同步縮小摩爾定律講的是技術(shù)密度倍增的趨勢迪納德定律講的是實現(xiàn)密度倍增的方法兩者統(tǒng)稱為“摩爾定律”等比列縮小是實現(xiàn)摩爾定律的方法18GateWiringn+sourcen+drainL/tox/W/xd/Voltage

V/P

substrate,

do*NASCALING:Voltage:Oxide:Wire

width:Gate

width:Diffusion:Substrate:V/

tox/

W/

L/

xd/*NARESULT:Higher

density:

~2Higher

speed:

~

Power/ckt:

~1/2Power

Density:

~ConstantPower

Density

=

Constant?190.111010010000.011Classic

Scalingtox(A)Vdd(V)0.1Ga ength

Lgate(m)DramaticallyIncreasing

ofPower

DensityPower

Density

≠

ConstantReasons

of

the

shiftUnacceptable

leakagecurrentHigher

voltage

implieshigher

performanceResult

of

the

shift2010110210310410510610710070

75

80

85

90

95

00

05

10

15

20

25UnscaledPower

Density1%DeviationAir

CoolingLimit“Perfect”

PowerDensity

ScalingLogic

Power

Density

(Watts/cm2)Why

Power

Density

Is

Important21Power

Consumption

is

key2224681012900010Module

Heat

Flux

(Watts/cm2)IBM360IBM370

IBM3033IBM4381IBM3081Fujisu

M380IBM3090CDC

Cyber

205Fujisu

M780NTTIBM3090SFujisu

VP2000IBMS9000BipolarCMOSApacheMercedPentium

IIIBM

RY4PulsarIBM

RY6IBM

RY7PentiumIVIBMRY5IBMGP?電熨斗的功率密度:5W/cm2Materials

and

Device23Signal

Integrity頻率越高，波長越短。當(dāng)天線的尺寸不波長處在同一量級的時候，天線將輻射和接受電磁波。今天的集成電路運行在GHz，信號完整性是個嚴(yán)峻的。24ENIAC:

Application

Specific

ComputerENIAC是一臺與為 軍方計算火

彈道軌跡設(shè)計的與用計算機。雖然具備一定的編程能力，但程序是事先預(yù)置好的。改變程序就要求改變硬件的連線結(jié)構(gòu)。嚴(yán)格意義上講，ENIAC丌是一臺通用計算機。ENIAC運行時，安排了一批年輕的女性

按照計算要求插拔眾多的接頭，以實現(xiàn)丌同的運算。工作十分繁瑣，出錯概率很大，效率很低。硬件的準(zhǔn)備時間大大超過實際的計算所需的時間。25The

Von ann

architecture

is

a

designmodel

for

a

stored-program

digital

computerthat

uses

a

central

processingunit

(CPU)

and

asingle

separate

storage

structure

(memory)

tohold

both

instructions

and

data.of

the

Von

ann’sCharacteristicsarchitecture:a)

memory;control

unit;arithmetic

logic

unit;input

/

output

interface.The

disadvantage

of

Von

annarchitecture:

shared

memory

for

instructionsand

data

with

one

data

bus

and

one

addressbus

between

processor

and

memory.Instructions

and

data

have

to

be

fetched

insequential

order

(known

as

the

Vonann

Bottleneck),

limiting

the

operationbandwidth.Von ann

Architecture26Instruction

=

Low

Efficiency取指運算結(jié)果指令地址有效讀使能數(shù)據(jù)有效寫入指令寄存器數(shù)據(jù)地址有效讀使能取操作數(shù)二數(shù)據(jù)有效寫入寄存器指令譯碼數(shù)據(jù)地址有效讀使能取操作數(shù)一數(shù)據(jù)有效寫入累加寄存器數(shù)據(jù)地址有效寫使能數(shù)據(jù)有效寫入

器完成一個運算需要大量的準(zhǔn)備工作想加快運算速度要就加快所有環(huán)節(jié)涉及大量對外部

器的操作信號傳辒需要涉及全局性的互連“性能墻”“

墻”“功耗墻”2+3=527Various

ArchitectureHarvardVLIWMulti-CoresMany-CoresDual-CoresMulti-threadsOut-of-orderExecutionMulti-IssuesPipeline2860年前，硬件很貴復(fù)用資源是必須的Hardware

=

Expensive29Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines30Performance,

Cost

and

Power提升性能是永恒的保證性能的前提下降低成本保證性能的前提下降低功耗保證性能和成本的前提下降低功耗保證性能和功耗的前提下降低成本導(dǎo)提致升功性耗能上必升然致增提成加升本資性上源能升，要導(dǎo)求致減降性少低能資成下源本降，要導(dǎo)求要降求低降成低本性通能常31Economy:

Heavy

InvestmentHuge

Investment

Stops

Investor16nm～12-15B

$22nm～8-10B

$32nm～5-7B

$45nm～3.5-5B$65nm～2.5-3B

$32Cost

Per

Transistor

Reduction(US

Dollar)Source：Industry

Restructuring,

IBS

Report,

2007Scaling-down

≠

Cost-down130nm2,45090nm2,81065nm3,

106降45nm4,024，32nm4,817要22nm6,63822nm之后，成本下已經(jīng)不是主要任務(wù)而提升性能成為主目標(biāo)。Economy:

Cost

Reduction33Source：Industry

Restructuring,

IBS

Report,

2007Lower

UtilizationEconomy:

R&D

Expense3435Only

a

few

high-end

chip

makers

todaycan

even

afford

the

exorbitant

cost

ofNEXT-GENERATION

RESEARCH

AND

DESIGN,

muchless

the

fabs

to

build

them.

將來

數(shù)高端設(shè)計公司可以負(fù)擔(dān)昂貴的研發(fā)費用，而更少的公司有能力制造新一代的產(chǎn)品。R.

Colin

Johnson,“IBM

Fellow:

Moore’s

Law

Defunct,”

EE

Times,

4/07/09Integrated

Circuit:

Game

of

Ri

anWally

Rhines,

Chairman

&

CEO,

Mentraphics,

August

2010Scaling-down

&

Vonn

ISAPerformance,

Cost

and

Power16nm22nm32nm45nm65nm12nm90nm130nmScaling-down

&

Vonann

ArchitecturePer

ChipScaling-down

&

Vonann

Architecture

&

PowerPer

Chip通用準(zhǔn)則：高性能、低功耗、低成本36More

Moore

and

More

Than

MooreSource：2007

ITRS37Physical

Limits:ParameterITRS

22nm

node

(2016)Physical

LimitMinimum

dimension9

nanometers1.5

nanometersFastest

switching

time150

femto-seconds40

femto-secondsPower

dissipation

limits:

“Device-at-the-physical-limit”

will

dissipateseveral

thousand

Watts/square-cmTechnological

Limits:

Pushing

CMOS

to

its

ultimaimits

requiresrevolutionary

materials

and

deviceinnovations

that

havesignificantscientific

and

engineering

barriersEconomic

Limits:

Implementing

all

the

technology

innovations

mayraise

manufacturing

and

development

costs

to

being

beyond

thereach

of

all

but

a

few

global

entities.Source:

G.

Scalise,

WSC2007Limits

of

CMOS

Technology38ASICSingle-ProcessorSoCDual-ProcessorSoCSoC

EraMPSoC

EraIPLogic1IPLogic1IPLogic1μPMemμPMemμPMemμPMemμPMemμPMemMemMemMemμPMemoryIP

Logic1IP

Logic2IP

Logic3IP

Logic4DSPμPMemoryIPLogic1IPLogic2IPLogic3IPLogic4IPLogicASIPASIPASIPIPLogic1MemMemMemDSPDSPDSP

ASIC

Era

198519952005Multiple-ProcessorSoC來源：

，CIC’2008

蘇州System

on

Programmable

Chip39Shared

MemorycacheprivateprivateprivateprivateMEMPeripheryChip

BussoftwarehardwareApplicationArchitecturePEDriversOperating

SystemRTOS-APIApplicationsArchitecture

DesigntimertimerBusCtrlI/O

INTCORE40全球大約有超出20萬名患者植入人工耳蝸，長時間持續(xù)供電是使用中遇到的最大問題。隨著3G服務(wù)的普及，規(guī)頻逐漸成為時尚一族的新寵，功耗成為最受關(guān)心的問題之一。Low

Power

Technology41頭盔安裝顯示器攜帶式電池組手指觸摸操作裝置平板顯示器/鍵盤Extreme

Low

Power

Design42器市場觃模約占IC總市場的22％，其中以DRAM和Flash為代表的容性

技術(shù)是當(dāng)前應(yīng)用的主流

技術(shù)。面向高性能計算的DRAM2010年發(fā)展到44nm/4Gb采用ZrO2-HfO2

MIM疊層電容單元面積6F22016年將發(fā)展到22nm/4F2面向高密度數(shù)據(jù)

的Flash2010年發(fā)展到32nm/32Gb采用2-3值浮柵

技術(shù)單元面積4F2/1.3F2(每位）2016年將發(fā)展到

18nm/4bMLCDRAMNAND-FlashSemiconductor

Memory43Top

ElectrodeAmorphousContactPCMaterialHeaterGSTFeRAM鐵電材料極性翻轉(zhuǎn)導(dǎo)致電容變化非電荷型容性器采用2T2C/1T1C結(jié)構(gòu)單元尺寸22-16

F2優(yōu)點:低壓、耐疲勞缺點:單元尺寸大、破壞性MRAM

磁性材料自旋極化翻轉(zhuǎn)導(dǎo)致巨磁電阻或磁隧穿結(jié)電流變化阻性

器采用1T1R/1D1R結(jié)構(gòu)單元尺寸45-20

F2優(yōu)點:低壓、耐疲勞缺點:尺寸、電流大PCRAM/RRAM熱（電壓）作用下材料結(jié)晶相（導(dǎo)電）變化阻性

器采用1T1R/1D1R結(jié)構(gòu)單元尺寸4-5

F2優(yōu)點:低壓、多值操作缺點:尺寸縮小后材料可靠性及耐疲勞性差New

Memory

Technology44Memory

TechnologyFilament機制的實驗證明:TEM

觀察到了TiO2

薄膜中Ti4O7Filament的“連通”不“斷裂”D.K.Kwon,

Nature

Nanotech,

5,

148,

201045RRAM在速度、功耗、低壓操作等方面均優(yōu)于PCM，其擦寫次數(shù)也達(dá)到了109（Flash是106）,目前制約其

產(chǎn)品化的問題是集成觃模。仍結(jié)構(gòu)和熱耗散的角度看，RRAM是最適于Scaling-down的一種結(jié)構(gòu)。目前制約其集成度提高的主要是TMO變阻單元的

“重復(fù)性”和“一致性”問題。RRAM的結(jié)構(gòu)50nm線寬的TiO2

Memristor（HP公司）Challenges

ofMemory46Comparison

of

Different

Memories技術(shù)DRAMFG-NORFG-NANDCTMFeRAMMRAMSTT-MRAMPRAMRRAM技術(shù)節(jié)點(nm)44-1845-2532-2225-10180-130130-6565-3245-18NA非揮發(fā)性NoYesYesYesYesYesYesYesYes單元尺寸(F2)6-49-115-4/1.34/1.022-164520-105-45/1.2位數(shù)122-42-411122-4讀速度(ns)~1010-30~50~50<20<20<20<50<20寫/擦速度(ns)~10104-103106-105105-10410-2010-2010-2050-120<100耐疲勞次數(shù)>1016105106-104106-104109-1015>3×1016>1012106-109NA功耗LowHighMedMedLowHighMedMedLow可縮小性MedNoMedYesNNMedYesYes1

主要參考ITRS-2009及近年來一些相關(guān)研究

；部分?jǐn)?shù)據(jù)為理論值或

值，而非實際

的數(shù)據(jù)；主要針對獨立式器進(jìn)行對比，上表未包括各種及特殊應(yīng)用；47電荷操作容性器的物理極限及統(tǒng)計學(xué)限制電容隨工藝縮小丌斷變小，

電荷下降，可靠性變差電容間耦合效應(yīng)急劇加劇，導(dǎo)致操作可控性下降器件漏電增加，信號完整性下降操作電壓受各種

介質(zhì)及絕緣介質(zhì)厚度限制難以降低22-16nm

DRAM技術(shù)4F2單元結(jié)構(gòu)技術(shù)及低功耗設(shè)計技術(shù)高介電材料及MIM電容技術(shù)及低漏電

晶體管技術(shù)工藝制造技術(shù)：光刻、金屬柵、良率控制等目前無可替代技術(shù)：STT-MRAM可縮小性尚達(dá)丌到要求22-16nm

NAND-Flash技術(shù)25nm以下（2012年）將必須改用電荷俘獲

技術(shù)（預(yù)計可到10-16nm）耐疲勞次數(shù)將下降到10K以下，要求研發(fā)12-32位糾錯技術(shù)可替代技術(shù)：4b-CTM+3DNOR-Flash在32-25nm將可能被CTM、PCRAM及RRAM等新型技術(shù)取代Challenges

of

Memory

Technology48Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines49General

Purpose

Integrated

Circuits50From

Single-core

to

Multi-coreSingle

core

processorPerformance

–

Clock

rate51Dual-core

processorPerformance

–

ResourcesFrom

Multi-core

to

Many-coreMulti-core

processorPerformance

–

Multi-task52Many-core

processorPerformance

–

ParallelizationHomogeneous

and

HeterogeneousSeungjin

Lee,

etc."A

345mWHeterogeneousMany-CoreProcessor

withanIn

ligentInference

Enginefor

Robust

ObjectRecognition",

ISSCC2010,

February

10,2010,

pp.

332-333Jinuk

Luke

Shin,

etc."A

40nm

16-Core128-Thread

CMTSPARC

SoCProcessor",

ISSCC2010,

February

8,2010,

pp.98-9953GranularityD.

Rossi,etc.

"A

Heterogeneous

Digital

Signal

Processor

Implementation

forDynamicallyReconfigurable

Computing",

CICC

2009,

pp.641

-

64432-bit54Inter-ConnectionsBus-connectCross-barNoCSegmentedhierarchical1-D2-D(mesh)55FPGA:

From

Simple

to

ComplexLogic: Field

Programmable

Gate

ArrayI/O

BlocksCLBsPIsDRAMDSPCPUBuffers…56I/O

BlocksCLBsPIsFPGA:

From

Logic

to

ProcessingLogic: Field

Programmable

Gate

ArrayProgrammable

LogicLogic

FunctionProgrammableFunctional

BlocksSignal

ProcessingComputing57Logic: Field

Programmable

Gate

ArrayHomogeneous

and

HeterogeneousCombination

of

differentFunctional

blocks58Combination

of

sameFunctional

blocksMany-Cores

vs.

FPGAConvergence: A

General

Trend?Many-core

Processor59High

PerformanceComplex

FPGA?Dynamic

Reconfigurable,Reprogrammable,Computing/Logic

ArrayDemand

to

RCPPerformance,

Cost,

Power

and

Flexibility名稱性能成本功耗靈活性ASIC極高低小差FPGA高較高較大較好CPU中高大極好RCP極高較低較小好ASIC:

Application

Specific

Integrated

CircuitFPGA:

Field

Programmable

Gate

ArrayCPU:

Central

Processing

UnitRCP:

Re-Configurable

Processor計算性能單位面積性能（MOPS/mm2）能耗效率（nJ/Operation）靈活性RISC一般<100~1極好DSP一般<100~1極好RISC多核高<100~1好DSP多核高<100~1好ASIC極高>1000~0.01差RCP極高~1000~0.03好6061Computation/Control

IntensiveReconfigurable

Computing:

DatapathIF

(condition

=

1)THENr1

=b

*b;r2=

a

*

c;r2

=r2

*4;r1

=r1

-

r2;IF

(r1

<

0)

THENstate

=

‘1’;ELSEstate

=

‘0’;

r3=

r1*

4;r3=

r3+

1;r3=

r3*

0.2;FOR

i

=

1

to

3LOOPr4

=

r1

/

r3;r3

=

r3

+

r4;r3

=r3

/

2;END

LOOP;r1

=

0

-

b;r2

=

a

+

a;r4=

r1+

r3;x1

=r4

/

r2;r5=

r1-

r3;x2

=

r5

/

r2;END

IF;END

IF;IF

(condition

=

1)THENCOMPUTATION

1;IF

(r1

<

0)

THENCOMPUTATION

2;ELSECOMPUTATION

3;FOR

i

=

1

to

3LOOPCOMPUTATION

4;ENDLOOP;COMPUTATION

5;END

IF;END

IF;COMPUTATION

1r1

=

b

*

b;r2

=

a

*

c;r2

=

r2

*

4;r1

=

r1

-

r2;COMPUTATION

2state

=

‘1’;COMPUTATION

3state

=

‘0’;

r3

=

r1

*

4;r3

=

r3

+

1;r3

=

r3

*

0.2;COMPUTATION

4r4

=

r1

/

r3;r3

=

r3

+

r4;r3

=

r3

/2;COMPUTATION

5

r1

=

0

-

b;r2

=

a

+

a;r4

=

r1

+

r3;x1

=

r4/r2;r5

=

r1

-

r3;x2

=

r5/r2;ComputationControlVon

annArchitectureArchitecture

Evolution62Universal

ArchitectureVon

annArchitectureInputOutputClockControlVectorsTest

DataDatapathMemoryControllerMemoryControl

Codes

ProgramThis

universal

architectureleads

to

different

structuresfor

ASIC

and

general

purposeprocessor.63ASP:

Datapath

and

ControllerDatapath

consists

in

resources,memories

and

interconnectionsDatapath

performs

functionalcalculation

according

toinputs.Datapath

operates

according

tocontrol-vectors

from

controller.Datapath

is

not

directly

controlledby

system

clock.Datapath

provides

necessary

test-data

tocontroller.Controller

consists

in

state

generatorand

control-vect

enerator.Controller

generates

control-vectorsaccording

to

test-data

and

data-flow.Controller

operates

according

tosystem

clock.ASP:

Application

SpecificProcessor

→

AISCAny

digital

system

can

becomposed

of

Datapath

andControllerASIC

Design:

High-Level

SynthesisInputOutputClockControlVectorsTest

DataDatapathMemoryControllerMemoryControl

Codes64ASIC

Design:

High-Level

SynthesisHardware:

High-Level

SynthesisHardwareDescriptionsOperation

SchedulingRegister

OptimizationResource

AllocationInterconnection

GenerationControl-Codes

GenerationState

GenerationFSM

DesignApplication

specified

architectureScheduling/allocation

during

designDepends

on

hardware

descriptionComponents

do

not

fully

connectedControl-Codes

cannot

be

changedState-Machine

is

not

programmed65InputOutputClockControlVectorsTest

DataDatapathMemoryControllerMemoryControl

Codes

ProgramGPP:

Datapath

and

ControllerGPP:

General

PurposeProcessor

→

MPUAny

processor

c

so

becomposed

of

Datapath

andControllerVon

annArchitectureDatapath

consists

in

resources,memories

and

interconnectionsDatapath

performs

functionalcalculation

according

toinputs.Datapath

operates

according

tocontrol-vectors

from

controller.Datapath

is

not

directly

controlledby

system

clock.Datapath

provides

necessary

test-data

tocontroller.Controller

consists

in

state

generatorand

control-vect

enerator.Controller

generates

control-vectorsaccording

to

test-data

and

program.Controller

operates

according

tosystem

clock.66General

Purpose

Processor

DesignSoftware:

High-Level

SynthesisApplicationProgramOperation

SchedulingRegister

OptimizationResource

AllocationInterconnection

GenerationControl-Codes

GenerationState

GenerationState

Machine

ProgrammingGeneral

purpose

architectureScheduling/allocation

during

compileinterconnection,

control-codes

andstate

are

generated

during

compileComponents

are

fully

connectedControl-Codes

can

be

changedState-Machineis

programmable67Datapath:

Uniform

ArchitectureReconfigurable

Computing+zx

yOperation

Operatorz=

x

+yVariableVariableVariableRegisterRegisterRegisterALU68RTL

StructureInput

BusOutput

BusALURegistersRegistersInput

BusOutput

BusRegistersALURegisters691-Dimension

Data-pathRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRegisterRTL

Architecture1-Dimension

Expansionx70Two-dimension

Expansion2-Dimension

Data-pathxy713-Dimension

Data-pathThree-dimension

Expansionxyz72Task-Flow

Map12367124567e

=

a

+

b;f

=

c

*

d;h

=

e

–

f;h

=

e

+

f;i=e

/

f;o1

=

g

*

h;o2

=

h

–

I;ab

cdefg4h5i3

73Memories

Map123671234567ab

cdefg4habcdef5ighie

=

a

+

b;f

=

c

*

d;h

=

e

–

f;h

=

e

+

f;i=e

/

f;o1

=g

*

h;o2

=

h

–

I;74Connections

ConfigurationInterconnections

among

operation

1,

operation

2and

operations

3,

operation

4,

operation

5

areconfigured

according

to

the

data

dependency.75abcdefghi1234567Power-GatingProcessors,

memories

andinterconnectionsthatarenot

used

will

bepowergated

in

order

to

decreasepower

consumption.7677ALU:

Multi-Function

UnitX-BusY-BusINPUTBUFFEROUTPUTBUFFERIN

InterfaceOUT

InterfaceContextStatusControllerContext

InterfaceIRQsController:

Programmable-FSMIF

(condition

=

1)

THENCOMPUTATION

1;IF

(r1

<

0)

THENCOMPUTATION

2;ELSECOMPUTATION3;FOR

i=1

to

3LOOPCOMPUTATION

4;ENDLOOP;COMPUTATION

5;END

IF;END

IF;43152i

≤3r1

≥0Computation

1Computation

2Computation

3Computation

4Computation

5i

>3r1

<0FSM:

Finite

State

MachineProgrammable78RISC

BasedProgrammable-FSMRB-PFSM:

1.

Read

current

state

from

State-MemoryDecide

next

state

and

generate

address

according

totest

data,

that

address

theData-Memory

andConfiguring-ContextOutput

the

data

and

configuring-contextRISCMemoryCompilerDatapathCompilerRISCState-MemoryData-MemoryConfiguring-ContextDatapathTest-DataTest-Data79Control-Flow

&

Configuring

ContextRegisterALURegisterRISCState

ControlState/Address

MemoryTest

DataGlobal

DataRegisterEn/DisableALU

Config.Connection

Config.Controller

DatapathGlobal-Data

MemoryConfiguring-ContextRegisterEnable/DisableALU-ContextConnection-ContextPower-ContextPower

Config.80Power

Consumption

ReductionOnly

one

row

works

each

timewhen

datapath

performscalculation.

Thus,

the

powerconsumption

of

datapath

isgreatly

reduced.81Multi-Task

Pipeline

ExecutionTask

1Task

2Task

3Task

4Tasks

areindependentNumber

oftasks

is

limitedby

the

size

ofdatapath82Basic

RequirementReconfigurable

ComputingNo

InstructionC

Language

ProgrammingDynamic

ReconfigurableLocalizing

CommunicationsLocalizing

MemoriesScalable

&

ExtendableNo

IPRIssuesExistingSoftwarePortingReducingMemoryWallImprovingFlexibilityHardwareFlexibilityReducingGlobalWires83Programming

LanguageHigh-Level

Programming

Language(Such

as:

ANSI

C)Int

main(void)func(…,

…){{…………func(…,

…)}……dct(…,

,,,)dct(…,…)……{…………}}ChallengesAvailable

softwareC

languagePointersLoopsRecursive

callVectormatrix….CompilerSyntax

CheckCode

ProfilingCode

TransformationCode

OptimizationData-Flow

GenerationTask

PartitioningTask

SchedulingAllocationConnection

SchemeMap

sEvaluationsContext

Generation84Dimension

Limited:

Task

MapTask

Partitioning

Task

Flow

GenerationTask

DependencyTask

SchedulingDatapath

AllocationMap

Scheme8586Partitioning

and

Deadlocka1a3a4a5a2inp

sv2sv13sv26sv33

sv39m6m7c1c2a8a9a12a11a15m13c3

a10m14c4a16a19a25a27inp

m21a18c5a22sv38m24a29c7a28sv18sv2_o

sv13_o

sv18_oa17a20m31a34a32c6a23sv18a26c8m30sv38a33sv26_o

sv33_o

sv38_o

sv39_o

out_psv39Task

Graph

Partitioning

(No

Deadlock)a1a3a4a5a2inp

sv2sv13sv26sv33

sv39m6m7c1c2a8a9a12a11a15m13c3

a10m14c4a16a19a25a27inp

m21a18c5a22sv38m24a29c7a28sv18sv2_o

sv13_o

sv18_oa17a20m31a34a32c6a23sv18a26c8m30sv38a33sv26_o

sv33_o

sv38_o

sv39_o

out_psv39Task

Graph

Partitioning

(Deadlock)RequirementsLess

interconnections(communication

cost)

between

sub-parts;Avoid

deadlock.Task

Graph

PartitioningGlobal

Datsinga1a3a4a5a2inp

sv2sv13sv26sv33sv39m6m7c1c2a8a9a12a11a15m13c3

a10m14c4a16a19a25a27inp

m21a18c5a22sv38m24a29c7a28sv18sv2_o

sv13_o

sv18_oa17a20m31a34a32c6a23sv18a26c8m30sv38a33sv26_o

sv33_o

sv38_o

sv39_o

out_psv39lobal

Data

MemoryCacheCacheGlobalDataMemoryCache87Operating

SystemMulti-Task

managementResource

managementTime

sharing

and

resource

sharingMulti-ControllerDynamic

Resource

allocationQueue-up88Integrated

Circuits

Golden

Moore

&

VonannNano-Electronics

EraGenerality

is

KingIntegrated

Circuits

and

ICTOutlines89ICT

=

(C

+

C)/(IC

+S)計算機通信集成電路經(jīng)濟(jì)超級計算機工作站個人計算機便攜式計算機掌上計算機有線通信光通信無線/移動通信網(wǎng)絡(luò)通信通信器信號處理器處理器可編程邏輯轉(zhuǎn)換器電路辦公數(shù)據(jù)庫操作系統(tǒng)中間件應(yīng)用905681013

14

141826222733465051556010277144132

137126149204166139

141

213248

2562492275%

2%27%46%-17%24%24%39%7%

2%

8%10%42%29%32%4%-9%-8%19%37%-32%1%28%18%7%

9%

3%-2.8%10%28%

28%

27%19%197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008Worldwide

Semiconductor

Market（B

USD）

Growth

Rate(%)Global

sales

of

semiconductors

were

severely

impacted

by

the

world-wide

economicturmoil

in

2008,

resulting

in

the

year-on-year

sales

drop

since

2001.Total

sales

for

2008

were

$249

billion

compared

to

$256

billion

in

2007,

a

decrease

of

2.8percent.Source：WSC

GAMS

Meeting

2009Global

Semi

Market:

1976-20089192364512059789733006701

1

.

7

%5

.

2

%1

5

.

2

%3

.

8

%1

4

.

2

%7

.

6

%9

.

0

%16%14%12%10%8%6%4%2%0%350000300000250000200000150000100000500000G

D

PGR

Y

2

YData

Source：National

Bureau

ofStatistics

(NBS)Source：Industry

Restructuring,IBS

Report,

2007GDP

of

China:

1978–2008

(Unit:

100M

RMB)GDP

vs.

Semi

Market:

1995-2007集成電路

和

是信息產(chǎn)業(yè)的基礎(chǔ)，沒有自主的

和自主

，就沒有自主產(chǎn)業(yè)

的

“心”和“魂”。“缺心少魂”的產(chǎn)業(yè)是人家

的附庸，沒有發(fā)展的自主權(quán)。近50年，世界主要強國的發(fā)展歷叱證明，必須擁有自己的

技術(shù)，尤其是集成電路和

這樣的

基礎(chǔ)產(chǎn)業(yè)。Source