ch06-7用Verilog描述時(shí)序邏輯電路

6.7.1

移位寄存器的Verilog建模

6.7.2

計(jì)數(shù)器的Verilog建模

6.7.3狀態(tài)轉(zhuǎn)換圖的Verilog建模

6.7.4數(shù)字鐘的Verilog建模

6.7用VerilogHDL描述時(shí)序邏輯電路

用行為級(jí)描述always描述一個(gè)４位雙向移位寄存器，有異步清零、同步置數(shù)、左移、右移和保持。功能同74xx194。6.7.1移位寄存器的Verilog建模moduleshift74x194(S1,S0,D,Dsl,Dsr,Q,CP,CR);

inputS1,S0; //控制輸入

inputDsl,Dsr; //串行輸入

inputCP,CR; //時(shí)鐘及清零

input[3:0]D;

//并行輸入

output[3:0]Q; //寄存器輸出

reg[3:0]Q;

6.7.1移位寄存器的Verilog建模

always@(posedgeCPornegedgeCR)

if(~CR)Q<=4'b0000;

else

case({S1,S0})

2‘b00:Q<=Q; //保持

2‘b01:Q<={Q[2:0],Dsr}; //右移

2‘b10:Q<={Dsl,Q[3:1]}; //左移

2‘b11:Q<=D;

//并行輸入

endcaseendmodule

6.7.2計(jì)數(shù)器的Verilog建模moduleupdowncount_beh#(parametern=4)(inputLoad,Up_down,En,CP,//輸入端口聲明input[n-1:0]D, //并行數(shù)據(jù)輸入outputreg[n-1:0]Q//數(shù)據(jù)輸出端口及變量數(shù)據(jù)類型聲明);integerdirection;//中間變量聲明用Verilog描述帶使能端和同步置數(shù)端的可逆4位二進(jìn)制計(jì)數(shù)器always@(posedgeCP)beginif(Up_down) direction<=1;

else direction<=-1;

if(Load) Q<=D; //Load=1,同步置數(shù)

elseif(En) Q<=Q+direction;//加1或減1

elseQ<=Q; //輸出保持不變endendmodule6.7.3狀態(tài)轉(zhuǎn)換圖的Verilog建模moduleMealy_sequence_detector(A,CP,CR,Y);inputA,CP,CR;outputY;regY; reg[1:0]current_state,next_state;parameterS0=2’b00,S1=2’b01,S2=2’b11;always@(negedgeCPornegedgeCR)beginif(~CR)current_state<=S0;

//在CR下降沿設(shè)s0為初態(tài)

elsecurrent_state<=next_state;end用Verilog描述狀態(tài)轉(zhuǎn)換圖非常方便，常用always或case語(yǔ)句。下面程序，第一個(gè)always語(yǔ)句描述狀態(tài)轉(zhuǎn)移6.7.3狀態(tài)轉(zhuǎn)換圖的Verilog建模always@(current_state,A)

//組合電路

begin

case(current_state)//準(zhǔn)備下一狀態(tài),電路輸出

Y=0;

S0:beginnext_state=(A==1)?S1:S0;end

S1:beginnext_state=(A==1)?S2:S0;end

S2:if(A==1)beginnext_state=S2;end

elsebeginY=1;next_state=S0;end