EDA實(shí)驗(yàn)報(bào)告 計(jì)數(shù)器及序列檢測(cè)器

EDA實(shí)驗(yàn)報(bào)告通信工程二班李桐20100820212實(shí)驗(yàn)?zāi)康模河?jì)數(shù)器的原理及應(yīng)用?；旌夏Ｊ降墓こ淘O(shè)計(jì)法的應(yīng)用。數(shù)碼管掃描電路的應(yīng)用。序列檢測(cè)器原理。Mealy型與Moore型狀態(tài)機(jī)原理。狀態(tài)圖輸入法。實(shí)驗(yàn)原理：計(jì)數(shù)器是一種常用的可統(tǒng)計(jì)時(shí)鐘脈沖個(gè)數(shù)的時(shí)序邏輯器件。計(jì)數(shù)器中的“數(shù)”是觸發(fā)器的狀態(tài)組合，即編碼。計(jì)數(shù)器循環(huán)一次所包含的狀態(tài)總數(shù)就稱作模。本次試驗(yàn)采用VHDL語言直接構(gòu)建一個(gè)202進(jìn)制計(jì)數(shù)器。狀態(tài)機(jī)是由一組狀態(tài)、一個(gè)初始狀態(tài)、輸入輸出和狀態(tài)轉(zhuǎn)換函數(shù)組成的時(shí)序電路。狀態(tài)機(jī)主要用來控制電路的狀態(tài)轉(zhuǎn)移，針對(duì)不同類型的狀態(tài)機(jī)，輸出可以由現(xiàn)態(tài)確定，也可以由現(xiàn)態(tài)及次態(tài)共同確定。按狀態(tài)機(jī)的信號(hào)輸出方式分類，可分為Mealy型狀態(tài)機(jī)和Moore型狀態(tài)機(jī)。Mealy型狀態(tài)機(jī)，次態(tài)和輸出均取決于現(xiàn)態(tài)和當(dāng)前輸入；Moore型狀態(tài)機(jī)，下一狀取決于當(dāng)前狀態(tài)和當(dāng)前輸入，但其輸出僅取決于當(dāng)前狀態(tài)。序列檢測(cè)器是用于從二進(jìn)制碼流中檢測(cè)出一組特定序列信號(hào)的時(shí)序電路。接受的序列信號(hào)與檢測(cè)器預(yù)設(shè)值變焦，相同則輸出為1，否則輸出為0。實(shí)驗(yàn)具體步驟：1.202進(jìn)制加法計(jì)數(shù)器(1).VHDL結(jié)構(gòu)式描述頂層(調(diào)用了202進(jìn)制加法計(jì)數(shù)器與七段譯碼器)libraryieee;useieee.std_logic_1164.all;entitycnt212_7segisport(clk,clrn,en,scan_clk:instd_logic;cout:outstd_logic;seg7:outstd_logic_vector(6downto0);wei:outstd_logic_vector(2downto0));endcnt212_7seg;architecturearchofcnt212_7segiscomponentcnt212isport(clk,clrn,En:instd_logic;cout:outstd_logic;b,s,g:outstd_logic_vector(3downto0));endcomponent;componentscan_led3_vhdisport(scan_clk,cnt_aclr:instd_logic;datab,datas,datag:instd_logic_vector(3downto0);seg7:outstd_logic_vector(6downto0);wei:outstd_logic_vector(2downto0));endcomponent;signalwdatab,wdatas,wdatag:std_logic_vector(3downto0);begincnt_212:cnt212portmap(clk,clrn,En,cout,wdatab,wdatas,wdatag);scan_led3:scan_led3_vhdportmap(scan_clk,(notclrn),wdatab,wdatas,wdatag,seg7,wei);endarch;(2).VHDL語言描述學(xué)號(hào)計(jì)數(shù)器(調(diào)用了10進(jìn)制加法計(jì)數(shù)器)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycnt212isport(clk,clrn,En:instd_logic;cout:outstd_logic;b,s,g:outstd_logic_vector(3downto0));endcnt212;architecturearchofcnt212iscomponentexp_cnt10isport(clk,clrn,En:instd_logic;cq:outstd_logic_vector(3downto0);cout:outstd_logic);endcomponent;componentdffport(d,clk,clrn:instd_logic;q:outstd_logic);endcomponent;signalcouts,coutg,coutb,q1,q2,lkaclr:std_logic;signalregb,regs,regg:std_logic_vector(3downto0);begincntg:exp_cnt10portmap(clk,(clrnandlkaclr),En,regg,coutg);dff1:dffportmap(coutg,clk,clrn,q1); --利用D觸發(fā)器實(shí)現(xiàn)進(jìn)位cnts:exp_cnt10portmap(q1,(clrnandlkaclr),En,regs,couts);dff2:dffportmap((coutsandcoutg),clk,clrn,q2); --利用D觸發(fā)器實(shí)現(xiàn)進(jìn)位cntb:exp_cnt10portmap(q2,(clrnandlkaclr),En,regb,coutb);lkaclr<='0'when(regb=x"2"andregs=x"1"andregg=x"2”)else--在此實(shí)現(xiàn)清零'1';cout<='1'when(regb=x"2"andregs=x"1"andregg=x"1”)else--在此使進(jìn)位為'1''0';b<=regb;s<=regs;g<=regg;endarch;⑶?VHDL語言描述10進(jìn)制加法計(jì)數(shù)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityexp_cnt10isport(clk,clrn,En:instd_logic;cq:outstd_logic_vector(3downto0);cout:outstd_logic);endexp_cnt10;architecturearchofexp_cnt10issignalcqi:std_logic_vector(3downto0);beginprocess(En,clk,clrn,cqi)beginifclrn='0'thencqi<="0000”;elsifclk'eventandclk='1'thenifEn='1'thenifcqi<9thencqi<=cqi+1;elsecqi<="0000”;endif;endif;endif;ifcqi=9thencout<='1';elsecout<='0';endif;cq<=cqi;endprocess;endarch;(4).VHDL語言描述七段譯碼器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityscan_led3_vhdisport(scan_clk,cnt_aclr:instd_logic;datab,datas,datag:instd_logic_vector(3downto0);seg7:outstd_logic_vector(6downto0);wei:outstd_logic_vector(2downto0));endscan_led3_vhd;architecturertlofscan_led3_vhdissignalseg_wire:std_logic_vector(3downto0);signalwei_wire:std_logic_vector(2downto0);typestis(k_L,k_R,ad_L);signalst_nxt:st;beginscan_st:process(scan_clk,cnt_aclr,st_nxt)beginifcnt_aclr='1'thenst_nxt<=k_L;elsif(scan_clk'eventandscan_clk='1')thencasest_nxtiswhenk_L=>st_nxt<=k_R;whenk_R=>st_nxt<=ad_L;whenad_L=>st_nxt<=k_L;endcase;endif;endprocess;scan_o:process(st_nxt,datab,datas,datag)begincasest_nxtiswhenk_L=>seg_wire<=datab;wei_wire<="100”;whenk_R=>seg_wire<=datas;wei_wire<="010";whenad_L=>seg_wire<=datag;wei_wire<="001";endcase;endprocess;seg7<="1111110"whenseg_wire=x"0"else”0110000"whenseg_wire=x"1"else"1101101"whenseg_wire=x"2"else"1111001"whenseg_wire=x"3"else"0110011"whenseg_wire=x"4"else"1011011"whenseg_wire=x"5"else"1011111"whenseg_wire=x"6"else"1110000"whenseg_wire=x"7"else"1111111"whenseg_wire=x"8"else"1111011"whenseg_wire=x"9"else"1110111"whenseg_wire=x"a"else"0011111"whenseg_wire=x"b"else"0001101"whenseg_wire=x"c"else"0111101"whenseg_wire=x"d"else"1001111"whenseg_wire=x"e"else"1000111"whenseg_wire=x"f"else"0000000";wei<=wei_wire;endrtl;⑸.頂層RTL電路scanIed3vhd:scanIedl3scanscanIed3vhd:scanIedl3scan(6).202進(jìn)制加法計(jì)數(shù)器RTL電路.頂層功能仿真波形圖elkI I I I I I I I I I Ie」沮 miffmiffmiffclrnencout sweiSCDCIDGDCDCLXIDCDCIDGDCDCIDGDCDCIDGDCDCIDGDCIXDGDCDCIDGDCDCIDGDCDCIDCDCDCIDGDC1□segTkiiiiii。 iqo^X111111。X。ii〔XiiiiiioX。ii以111111QX】iopC111111。X】iQpC^11111。X】。。X111111ii111111。"^11iiiiiiqX111X111111。*111乂111111(.202進(jìn)制加法計(jì)數(shù)器功能仿真波形圖elkclrnelkclrnartb國，gcoutrn1X 2 X 09X 0 X1X 0 X1如圖所示成功實(shí)現(xiàn)了202進(jìn)制.管腳分配及下載驗(yàn)證

2.序列檢測(cè)器(1).1110010序列檢測(cè)器的VHDL設(shè)計(jì)狀態(tài)轉(zhuǎn)換表現(xiàn)態(tài)輸入0時(shí)次態(tài)/輸出輸入1時(shí)次態(tài)/輸出S0S0/0S1/0S1S0/0S2/0S2S0/0S3/0S3S4/0S3/0S4S5/0S1/0S5S0/0S6/0S6S0/1S2/0(2).用狀態(tài)圖輸入法實(shí)現(xiàn)序列檢測(cè)器StateMachineWizard:General[page1of4]-Whichresetmodedoyouwanttouse?CSynchronousAsynchronousVResetisactive-highrRegistertheoutputportsNext> |Finish| 取.消選擇復(fù)位reset信號(hào)為異步，高電平有效，輸出端無寄存器。States欄中輸入狀態(tài)名稱s0~s6。Inputports欄中輸入時(shí)鐘信號(hào)，clock，復(fù)位信號(hào)reset以及串行數(shù)據(jù)輸入信號(hào)din。

狀態(tài)機(jī)設(shè)計(jì)圖dinI"""""""""""""""""""生成的VHDL語言注意要添加clockout代碼顯示CLOCK信號(hào)LIBRARYieee;USEieee.std_logic_1164.all;ENTITYexp_detect3ISPORT(clock:INSTD_LOGIC;reset:INSTD_LOGIC:='0';din:INSTD_LOGIC:='0';clockout,z:OUTSTD_LOGIC);ENDexp_detect3;ARCHITECTUREBEHAVIOROFexp_detect3ISTYPEtype_fstateIS(s0,s1,s2,s3,s4,s5,s6);SIGNALfstate:type_fstate;SIGNALreg_fstate:type_fstate;BEGINPROCESS(clock,reset,reg_fstate)BEGINIF(reset='1')THENfstate<=s0;ELSIF(clock='1'ANDclock'event)THENfstate<=reg_fstate;ENDIF;ENDPROCESS;PROCESS(fstate,din)BEGINz<='0';CASEfstateISWHENs0=>IF((din='1'))THENreg_fstate<=s1;ELSIF(NOT((din='1')))THENreg_fstate<=s0;--Inserting'else'blocktopreventlatchinferenceELSEreg_fstate<=s0;ENDIF;WHENs1=>IF((din='1'))THENreg_fstate<=s2;ELSIF(NOT((din='1')))THENreg_fstate<=s0;--Inserting'else'blocktopreventlatchinferenceELSEreg_fstate<=s1;ENDIF;WHENs2=>IF((din='1'))THENreg_fstate<=s3;ELSIF(NOT((din='1')))THENreg_fstate<=s0;--Inserting'else'blocktopreventlatchinferenceELSEreg_fstate<=s2;ENDIF;WHENs3=>IF((din='1'))THENreg_fstate<=s3;ELSIF(NOT((din='1')))THENreg_fstate<=s4;--Inserting'else'blocktopreventlatchinferenceELSEreg_fstate<=s3;ENDIF;WHENs4=>IF((din='1'))THENreg_fstate<=s1;ELSIF(NOT((din='1')))THENreg_fstate<=s5;--Inserting'else'blocktopreventlatchinferenceELSEreg_fstate<=s4;ENDIF;WHENs5=>IF((din='1'))THENreg_fstate<=s6;ELSIF(NOT((din='1'