級(jí)計(jì)組實(shí)驗(yàn)3報(bào)告

：一、實(shí)驗(yàn)要實(shí)驗(yàn)名簡(jiǎn)單的類MIPS周期處理器制器實(shí)驗(yàn)?zāi)坷斫釩PU控制器，ALU實(shí)驗(yàn)范ISESpartan-3E實(shí)驗(yàn)板的使用VerilogHDL行邏輯設(shè)CPU器的實(shí)現(xiàn)5．ALU現(xiàn)二、實(shí)驗(yàn)原理主控制模塊（CTR模塊主控制單元輸入為指令的opCode字段，即操作碼。操作碼經(jīng)過(guò)主控制單元的譯碼ALUCtrDataMemoryRegisters，Muxs部件輸出正確的控制信號(hào)。ALU模塊ALUCtr（ALUCtrAluCtr根據(jù)主控制器的ALUOp來(lái)判斷指令類型。根據(jù)指令的后6位區(qū)分R型指令。綜合這兩種輸入，控制ALU正確的ALU模根據(jù)aluCtr，對(duì)兩個(gè)輸入做對(duì)應(yīng)的操作。aluRes輸出結(jié)果。如果是減法操作，若結(jié)果為0，zero出置為1.輸入：input132bit),，input2(32bit)，aluCtr輸出：zero(1bit)，aluRes三、實(shí)驗(yàn)程moduleinput[5:0]opCode,outputregDst,outputaluSrc,

branch=0;aluOp=2'b00;jump=1;

memRead=memWrite=branch=0;aluOp=2'b00;outputregWrite,

jump=outputmemRead,outputmemWrite,outputbranch,output[1:0]aluOp,outputjumpregregDst;regregregWrite;

regDst=aluSrc=memToReg=regWrite=memRead=memWrite=branch=0;aluOp=2'b10;jump=0;

aluSrc=regWrite=memRead=memWrite=branch=1;aluOp=2'b01;jump=0;regmemRead;regmemWrite;regbranch;reg[1:0]aluOp;regjump;always@(opCode)caseregDst=aluSrc=memToReg=regWrite=memRead=memWrite=

regDst=aluSrc=memToReg=regWrite=memRead=memWrite=branch=0;aluOp=2'b00;jump=0;aluSrc=regWrite=

regDst=aluSrc=memToReg=regWrite=memRead=memWrite=branch=0;aluOp=2'b00;jump=0;moduleALUCtr(aluOp,funct,aluCtr);output[3:0]aluCtr;input[5:0]input[1:0]reg[3:0]always@(aluOporfunct) ({aluOp,funct})

8'b00xxxxxx:aluCtr=4'b0010;8'bx1xxxxxx:aluCtr=4'b0110;8'b1xxx0000:aluCtr=4'b0010;8'b1xxx0010:aluCtr=4'b0110;8'b1xxx0100:aluCtr=4'b0000;8'b1xxx0101:aluCtr=4'b0001;8'b1xxx1010:aluCtr=moduleAlu(input1,input2,aluCtr,zero, input[31:0]input[31:0]

zero=zero=input[3:0]aluCtr;outputzero;output[31:0]aluRes;regzero;reg[31:0]always@(input1orinput2orif(aluCtr==aluRes=input1+input2;elseif(aluCtr==4'b0110)aluRes=input1-input2;if(aluRes==0)

elseif(aluCtr==aluRes=input1&input2;elseif(aluCtr==4'b0001)aluRes=input1|input2;elseif(aluCtr==4'b0111)if(input1<input2)aluRes=1;aluRes=elseif(aluCt