基于quartus2的mealy機(jī)類型控制adc0809采樣的狀態(tài)機(jī)

------------------------------------------------------------------------基于quartus2的mealy機(jī)類型控制adc0809采樣的狀態(tài)機(jī)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYADC0809ISPORT(D:INSTD_LOGIC_VECTOR(7DOWNTO0);CLK,RST:INSTD_LOGIC; EOC:INSTD_LOGIC; ALE:OUTSTD_LOGIC; START,OE:OUTSTD_LOGIC; ADDA,LOCK_T:OUTSTD_LOGIC; Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDADC0809;--------------跟moore型一樣；ARCHITECTUREBEHAVOFADC0809ISTYPESTATESIS(S0,S1,S2,S3,S4);SIGNALPST:STATES;--------------跟moore型不同，因?yàn)槭怯奢斎胄盘?hào)eoc控制狀態(tài)轉(zhuǎn)變，所以SIGNALREGL:STD_LOGIC_VECTOR(7DOWNTO0);只需一個(gè)pst狀態(tài)信號(hào)；SIGNALLOCK:STD_LOGIC;BEGINADDA<='0';LOCK_T<=LOCK;REGCOM:PROCESS(CLK,RST,PST,EOC) BEGIN--------------regcom進(jìn)程是一個(gè)時(shí)序與組合混合型進(jìn)程；IFRST='1'THENPST<=S0;ELSIFRISING_EDGE(CLK)THENCASEPSTIS WHENS0=>IFEOC='1'THENPST<=S1;ELSEPST<=S0;ENDIF; WHENS1=>IFEOC='0'THENPST<=S2;ELSEPST<=S1;ENDIF; WHENS2=>IFEOC='1'THENPST<=S3;ELSEPST<=S2;ENDIF; WHENS3=>IFEOC='1'THENPST<=S4;ELSEPST<=S3;ENDIF; WHENS4=>IFEOC='1'THENPST<=S0;ELSEPST<=S4;ENDIF; WHENOTHERS=>PST<=S0;--------------由eoc信號(hào)控制狀態(tài)轉(zhuǎn)變，如果eoc與當(dāng)前狀態(tài)下eoc的值一 ENDCASE;ENDIF;致，就轉(zhuǎn)到下一態(tài)；其中狀態(tài)2中eoc=‘0’表示正在轉(zhuǎn)換， ENDPROCESSREGCOM;eoc=’1‘表示轉(zhuǎn)換結(jié)束；COM:PROCESS(PST) BEGIN--------------com進(jìn)程主控組合進(jìn)程；CASEPSTISWHENS0=>ALE<='0';START<='0';OE<='0';LOCK<='0';WHENS1=>ALE<='1';START<='1';OE<='0';LOCK<='0';WHENS2=>ALE<='0';START<='0';OE<='0';LOCK<='0';WHENS3=>ALE<='0';START<='0';OE<='1';LOCK<='0';WHENS4=>ALE<='0';START<='0';OE<='1';LOCK<='1';WHENOTHERS=>ALE<='0';START<='0';OE<='0';LOCK<='0';ENDCASE;ENDPROCESSCOM;LATCH1:PROCESS(LOCK)BEGIN--------------鎖存器進(jìn)程latch1；IFLOCK='1'ANDLOCK'EVENTTHENREGL<=D;ENDIF; ENDPROCESSLATCH1; Q<=REGL; ENDBEHAV;--------------