用VHDL語言設(shè)計555壓控振蕩器測頻率

..>實驗五利用壓控振蕩器測量電壓一、實驗?zāi)康摹?〕以555定時器為根底設(shè)計壓控振蕩器〔2〕設(shè)計一個具有如下功能的簡易頻率計。1.可以測量壓控振蕩器產(chǎn)生的頻率，用4位數(shù)碼管顯示2.測量結(jié)果直接用十進制數(shù)值顯示3.被測信號是壓控振蕩器產(chǎn)生的方波脈沖信號，根據(jù)設(shè)計的壓控振蕩器確定電壓值4.具有超量程警告〔可以用LED燈顯示〕二、實驗設(shè)備與器材〔1〕計算機：QuartusⅡ軟件；〔2〕硬件：CycloneDE0-CVFPGA開發(fā)平臺、555定時器、電阻、電容、可變電阻三、利用Multisim搭建仿真電路四、實驗程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--計數(shù)器entityt10isport(rst,f*,ena:instd_logic;cout:outstd_logic;outy:outstd_logic_vector(3downto0));endt10;architecturebehvoft10isbeginprocess(rst,ena,f*)--定義變量--<=是對信號賦值；而:=是對變量進展賦值variablecqi:std_logic_vector(3downto0);begin--others=>'0'是對數(shù)組cqi所有元素賦值0ifrst='1'thencqi:=(others=>'0');elsiff*'eventandf*='1'thenifena='1'thenifcqi<9thencqi:=cqi+1;cout<='0';elsifcqi=9thencqi:=(others=>'0');cout<='1';endif;elsifena='0'thencqi:=(others=>'0');endif;endif;outy<=cqi;endprocess;endbehv;--4位10進計數(shù)器libraryieee;useieee.std_logic_1164.all;entityt10_4isport(f*,rst,ena,clk:instd_logic; d:outstd_logic_vector(15downto0);led_a:outstd_logic);endentity;architectureoneoft10_4iscomponentt10port(rst,f*,ena:instd_logic;cout:outstd_logic;outy:outstd_logic_vector(3downto0));endcomponent;componentled_heheport(ena,clk:instd_logic;q:outstd_logic);endcomponent;signale:std_logic_vector(3downto0);begin--整體使用一樣的rst和ena，f*作為進位使用。u1:cnt10portmap(f*=>f*,rst=>rst,ena=>ena,cout=>e(0),outy=>d(3downto0));u2:cnt10portmap(f*=>e(0),rst=>rst,ena=>ena,cout=>e(1),outy=>d(7downto4));u3:cnt10portmap(f*=>e(1),rst=>rst,ena=>ena,cout=>e(2),outy=>d(11downto8));u4:cnt10portmap(f*=>e(2),rst=>rst,ena=>ena,cout=>e(3),outy=>d(15downto12));u5:led_heheportmap(ena=>e(3),clk=>clk,q=>led_a);endarchitectureone;--16位鎖存器latch=閂libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitylatch4isport(d:instd_logic_vector(15downto0);ena,clk:instd_logic;q:outstd_logic_vector(15downto0));endlatch4;architectureoneoflatch4isbeginprocess(clk,ena,d)variablecqi:std_logic_vector(15downto0);beginifena='0'thencqi:=cqi;---ena=0鎖存上次的數(shù)據(jù)elsifclk'eventandclk='1'thencqi:=d;---clk=1&&ena=1計入新數(shù)據(jù)endif;q<=cqi;endprocess;endone;--報警ledhehelibraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityled_heheisport(ena,clk:instd_logic;q:outstd_logic);endled_hehe;architectureoneofled_heheisbeginprocess(clk,ena)variablecqi:std_logic;beginifena='0'thencqi:=cqi;---ena=0鎖存上次的數(shù)據(jù)elsifclk'eventandclk='1'thencqi:=notcqi;---clk=1&&ena=1計入新數(shù)據(jù)endif;q<=cqi;endprocess;endone;--LED控制模塊(數(shù)碼管controller)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityled_controllerisport(d:instd_logic_vector(3downto0);a:outstd_logic_vector(6downto0));endled_controller;architectureoneofled_controllerisbeginprocess(d)begincasediswhen"0000"=>a<="1000000";when"0001"=>a<="1111001";when"0010"=>a<="0100100";when"0011"=>a<="0110000";when"0100"=>a<="0011001";when"0101"=>a<="0010010";when"0110"=>a<="0000010";when"0111"=>a<="1111000";when"1000"=>a<="0000000";when"1001"=>a<="0010000";when"1010"=>a<="0001000";when"1011"=>a<="0000011";when"1100"=>a<="1000110";when"1101"=>a<="0100001";when"1110"=>a<="0000110";when"1111"=>a<="0001110";whenothers=>null;endcase;endprocess;end;--控制模塊(每隔一次clk，就翻轉(zhuǎn)ena和rst)libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycontrolisport(clk:instd_logic;rst,ena:outstd_logic);endcontrol;architecturebehvofcontrolisbeginprocess(clk)variablecqi:std_logic_vector(2downto0);beginifclk'eventandclk='1'thenifcqi<1thencqi:=cqi+1;ena<='1';rst<='0';elsifcqi=1thencqi:=(others=>'0');ena<='0';rst<='1';endif;endif;endprocess;endbehv;--時鐘〔1hz〕發(fā)生器libraryieee;useieee.std_logic_1164.all;entityfreq_divisport(clk:instd_logic;clk_out:outstd_logic);endfreq_div;architecturefwmoffreq_divisconstantm:integer:=25000;signaltmp:std_logic;beginprocess(clk,tmp)variablecout:integer:=0;beginifclk'eventandclk='1'thencout:=cout+1;ifcout<=mthentmp<='0';elsifcout<m*2thentmp<='1';elsecout:=0;endif;endif;endprocess;clk_out<=tmp;endfwm;--總體例化語句：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;--clk是50hz的板載時鐘信號，即參考信號，而f*才是測量的輸入信號entityvocisport(clk:instd_logic; f*:instd_logic;ledout:outstd_logic_vector(28downto0));---數(shù)碼管7*4endentity;architectureoneofvociscomponentfreq_divport(clk:instd_logic;clk_out:outstd_logic);endcomponent;componentcontrolport(clk:instd_logic;rst,ena:outstd_logic);endcomponent;componentt10_4port(clk,f*,rst,ena:instd_logic; d:outstd_logic_vector(15downto0);led_a:outstd_logic);endcomponent;componentlatch4port(d:instd_logic_vector(15downto0);ena,clk:instd_logic;q:outstd_logic_vector(15downto0));endcomponent;componentled_controllerport(d:instd_logic_vector(3downto0);a:outstd_logic_vector(6downto0));endcomponent;signal*,z:std_logic;signalg,h:std_logic_vector(15downto0);signalleds:std_logic_vector(28downto0);signalclk_base:std_logic;beginu1:freq_divportmap(clk=>clk,clk_out=>clk_base);u2:controlportmap(clk=>clk_base,ena=>*,rst=>z);u3:t10_4portmap(f*=>f*,rst=>z,ena=>*,d=>g,led_a=>leds(28),clk=>clk_base);u4:latch4portmap(clk=>clk_base,ena=>*,d=>g,q=>h);u5:led_controll