集成電路設(shè)計(jì)CAD-EDA工具實(shí)用教程1-Spe課件

Spectre–Verilog

混合信號(hào)仿真共27頁(yè)1幾家EDA軟件公司1、Cadence2、Synopsys（收購(gòu)Avanti）3、MentorGraphics4、Silvaco5、SpringSoft共27頁(yè)2SPICE仿真器SPICE:

ageneral-purposeanalogcircuitsimulatordevelopedbytheUniversityofCalifornia,Berkeley.ItisusedfornonlinearDC,nonlineartransient,andlinearACanalysis.Hspice:ageneral-purposecircuitsimulatorfromAvanti.Ithasanextensivesetofbuilt-indevicemodels,includingmodelsforsmallgeometryMOSFETsandMESFETs.TheprogramiscompatiblewithSPICEinputformats.CadencesupportsalibraryofprimitivesandafullinterfaceforHspice.Spectre:SPICE-alikeanalogsimulatordevelopedbyCadence.

共27頁(yè)3高精度模擬/射頻電路仿真器1、Spectre/SpectreRF(Cadence)2、Hspice/HspiceRF(Synopsys)3、Ads(Agilent主要針對(duì)RF)4、Eldo(MentorGraphics)5、Saber(Synopsys)共27頁(yè)4數(shù)?；旌闲盘?hào)仿真器1、Spectre-Verilog(Cadence)2、SMASH(DolphinIntegration)3、Eldo(MentorGraphics)4、Harmony(Silvaco)5、Saber(Synopsys)WhyMixed-SignalSimulation?共27頁(yè)5SystemintheRealWorld共27頁(yè)6MostlyAppliedMethodof

Mixed-SignalDesign系統(tǒng)分成若干個(gè)芯片，每個(gè)芯片分開設(shè)計(jì)，再經(jīng)電路板整合?；蛘哂肧oC實(shí)現(xiàn)。共27頁(yè)7Integrated

Mixed-SignalDesign共27頁(yè)8Mixed-SignalSimulator的基本結(jié)構(gòu)以模擬電路仿真器為核心在處理數(shù)?；旌想娐窌r(shí)將數(shù)字部分等效為相應(yīng)的簡(jiǎn)化的模擬電路、或者采用解析函數(shù)來(lái)表示邏輯模塊的行為，然后對(duì)整個(gè)系統(tǒng)采用模擬電路的方法進(jìn)行模擬。優(yōu)點(diǎn)：模擬結(jié)果精確、能處理的電路規(guī)模比較大，模擬速度也有顯著提高。缺點(diǎn)：比邏輯模擬器還是慢很多。同時(shí)包含模擬和數(shù)字兩個(gè)仿真核處理速度快，能處理的電路規(guī)模極大，但需要解決模擬仿真核和數(shù)字仿真核之間的通信問(wèn)題；另外，由于數(shù)字邏輯仿真器和模擬仿真器的輸入、輸出數(shù)據(jù)是不一樣的，還必須在模擬仿真核和數(shù)字仿真核之間實(shí)現(xiàn)模擬信號(hào)和數(shù)字信號(hào)的相互轉(zhuǎn)換。Q&A共27頁(yè)9CreatingAnalogBlockCreatetheschematicviewofanalogblock,andcreateasymbolviewforcelluse共27頁(yè)10CreatingDigitalBlock共27頁(yè)11CreatingaMixed-SignalSchematic共27頁(yè)12CreateConfigViewforSimulationThemixed-signalsimulationhierarchyiscontrolledbyHierarchy-Editorwhichmustbedefinedwithconfig

viewcellnameistopcircuitnameforsimulationviewnamewillbesetasconfigUseCreateNewFiletocreateanewconfig

viewwithHierarchy-Editor共27頁(yè)13SetNewConfiguration1.ChooseUseTemplatesampleinformation2.ChoosespetreVerilog1233.Changetheviewnametoschematicforsimulation4.ClickOK共27頁(yè)14OpentheSchematicVersionofConfigViewOpentheschematicversionoftheconfig

viewofmix

fromtheLibrarymanager共27頁(yè)15SetBlockPartition開啟hierarchyeditor設(shè)定所使用的cellview顯示所使用的cellview及其顏色設(shè)定Schematiceditor中的Hierarchy-Editor及Mixed-Signal兩項(xiàng)Menu是由菜單Tools->MixedSignalOpts.而產(chǎn)生的共27頁(yè)16CheckBlockPartitionChangeanalog&digitalstopviewstomatchthestopviewsinyourhierarchyeditor(asbelow)共27頁(yè)17CheckPartitionResults設(shè)定顯示的顏色及項(xiàng)目顯示所有模塊劃分的結(jié)果顯示模擬電路模塊顯示數(shù)字電路模塊顯示混合信號(hào)電路模塊顯示無(wú)法歸類的電路模塊清除所有顯示內(nèi)容共27頁(yè)18PartitionRequirementThedesignmustcontainatleastoneanalogcomponent.Thedesignmustcontainatleastonedigitalcomponent.Theremustbewithatleastoneinterfacenet.Analogstimulidefinedintheanalogstimulifilecannotbeusedtodrivedigitalnet.Digitalstimulidefinedinthedigitalstimulifilecannotbeusedtodriveanalognet.Anyinterfacenetmustbeidentifiedbeforenetlisting.共27頁(yè)19Setuptheanalog/digitalinterfaceSelect:Mixed-Signal-->InterfaceElements-->Instancethistoolisusedtoconfigurehowthedigitalblockreadsanaloginputsandhowdigitaloutputsareseenbyanalogcells(effectiveA/DandD/A).共27頁(yè)20Setuptheanalog/digitalinterfaceMOS_a2d:A2D_V0低電平

A2D_V1高電平

A2D_TX：voltagebetweenV0andV1afterTXwillyieldalogicXMOS_d2a：

ModelParametersD2A_VL:inputlowvoltageD2A_VH:inputhighvoltageD2A_TR:risetimeforlowtohighD2A_TF:falltimeforhightolow共27頁(yè)21SetupMenuinAnalogEnvironmentWithSetupwindowtodefinesimulationinitializationsetupChoosethesimulator?Definedevicemodellibrary?Definetemperature……共27頁(yè)22ChoosingSimulator/Directory/Host選擇SpectreVerilog共27頁(yè)23ChooseAnalysisTypeInvoketheanalysissettingwindowForMixed-Signalsimulation,onlytran

ismeaningfulSetthesimulationtimeCheckthi