寫給小白們fpga入門設計實驗

/12012-11-04Copyright(C)2012-20xxCrazyBingo歸Bingo所有，請注明出處《寫給小白們的FPGA設計實驗 寫面的 3內(nèi) 程 結果（問題，解決，體會 Lab2：4位減法、加法器設 8內(nèi) 程 結果（問題，解決，體會 Lab3：三位二進制乘法器設 內(nèi) 程 結果（問題，解決，體會 Lab4：序列檢測器設 內(nèi) 程 結果（問題，解決，體會 Lab5：變模計數(shù)器設 內(nèi) 程 結果（問題，解決，體會 Lab6：流水燈設 內(nèi) 程 結果（問題，解決，體會 Lab7：簡易電子時鐘設 內(nèi) 程 結果（問題，解決，體會 b：簡易計算器設計 內(nèi) 程 結果（問題，解決，體會 0-510……”再睡夢中著同樣的過去，日復一日，還有2年多……““開始走在一些人之上，開始NB，要散發(fā)的力量，必先經(jīng)歷的洗禮！再次，整理寫給們的FPGA設計實驗，希望對有用！當然如果你不是設計基于AlDE2-35開發(fā)平臺，針對板載LCD1602字符顯示器，通過字燈ASCII碼顯示。FPGAMCU有所不同。500KHzLCD1602。如下圖所示，LCD_EN的parameter[127:0]line_rom1="IamCrazyBingo!";parameter[127:0]line_rom2="oWorld*^_^*";module(

//lcd [127:0]line_rom1="IamCrazyBingo!"; [127:0]line_rom2="oreg always@(posedgeclkornegedgerst_n)cnt<=

cnt<=cnt+ lcd_on=1'b1; lcd_blon=1'b1; lcd_en=cnt[15];//lcdenable,keepsametime lcd_rw=1'b0; //writeonlywirecmd_flag=(cnt==16'h7FFF)?1'b1://Graycode:40 ////lcdparameterDISP_SET= //disymode DISP_OFF= //offdisy CLR_SCR= //clearthelcd CURSOR_SET1= //cursorset CURSOR_SET2 //on y,cursor// y1thROW1_ADDR // y2thROW2_ADDR reg[5:0]current_state,//FSM:always@(posedgeclkornegedgerst_n)current_state<=

elsecurrent_state<=//FSM:always2//lcd next_state=DISP_SET; next_state=DISP_OFF; next_state=CLR_SCR; next_state=CURSOR_SET1; next_state=CURSOR_SET2; next_state=ROW1_ADDR;// y1th next_state=ROW1_0; next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state=ROW1_F; //disy2th next_state=ROW2_0; next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state= next_state=ROW2_F; next_state=IDLE;//FSM:always@(posedgeclkornegedgerst_n)lcd_rs<=0;lcd_data<=8'hXX;//writestatement lcd_rs<=0;//lcd lcd_rs<=0;//statement lcd_rs<=0;//statement lcd_rs<=0;//statement lcd_rs<=0;//statement lcd_rs<=0;// y1th lcd_rs<=0;//statement lcd_rs<=1;//record lcd_rs<=1; lcd_rs<=1; lcd_rs<=1; lcd_rs<=1; lcd_rs<=1; lcd_rs<=1;ROW1_7:lcd_rs<=1;//recordROW1_8:lcd_rs<=1;//recordROW1_9:lcd_rs<=1;//recordROW1_A:lcd_rs<=1;//recordROW1_B:lcd_rs<=1;//recordROW1_C:lcd_rs<=1;//recordROW1_D:lcd_rs<=1;//recordROW1_E:lcd_rs<=1;//recordROW1_F:lcd_rs<=1;//disy2th lcd_rs<=0;//statement lcd_rs<=1;//record lcd_rs<=1;//record //writelcd_data lcd_data<=//lcd lcd_data<=8'h38; //set16X2,5X7,8bits lcd_data<=8'h08; //offdisy lcd_data<=8'h01; //clearlcd lcd_data<=8'h06; //cursorset lcd_data<= //ondis

ROW1_0:lcd_data<=line_rom1[127:120];ROW1_1:lcd_data<=line_rom1[119:112];ROW1_2:lcd_data<=line_rom1[111:104];ROW1_3:lcd_data<=line_rom1[103:96];ROW1_4:lcd_data<=line_rom1[95:88];ROW1_5:lcd_data<=line_rom1[87:80];ROW1_6:lcd_data<=line_rom1[79:72];ROW1_7:lcd_data<=line_rom1[71:64];ROW1_8:lcd_data<=line_rom1[63:56];ROW1_9:lcd_data<=line_rom1[55:48];ROW1_A:lcd_data<=line_rom1[47:40];ROW1_B:lcd_data<=line_rom1[39:32];ROW1_C:lcd_data<=line_rom1[31:24];ROW1_D:lcd_data<=line_rom1[23:16];ROW1_E:lcd_data<=line_rom1[15:8];ROW1_F:lcd_data<=line_rom1[7://disy2thROW2_ADDR:lcd_data<=ROW2_0:lcd_data<=line_rom2[127:120];ROW2_1:lcd_data<=line_rom2[119:112];ROW2_2:lcd_data<=line_rom2[111:104];ROW2_3:lcd_data<=line_rom2[103:96];ROW2_4:lcd_data<=line_rom2[95:88];ROW2_5:lcd_data<=line_rom2[87:80];ROW2_6:lcd_data<=line_rom2[79:72];ROW2_7:lcd_data<=line_rom2[71:64];ROW2_8:lcd_data<=line_rom2[63:56];ROW2_9:lcd_data<=line_rom2[55:48];ROW2_A:lcd_data<=line_rom2[47:40];ROW2_B:lcd_data<=line_rom2[39:32];ROW2_C:lcd_data<=line_rom2[31:24];ROW2_D:lcd_data<=line_rom2[23:16];ROW2_E:lcd_data<=line_rom2[15:8];ROW2_F:lcd_data<=line_rom2[7:0];1602的驅(qū)動時序相對于硬件描述語言而言比較復雜，需1602的驅(qū)動時序，最后通過不斷的刷屏來實現(xiàn)字符的顯示法器，最后結果通過QuartusII的仿真給出結果。VerilogHDL硬件描述語言。描述加法、減法算法，包括了進位Adder_4bits carry_in//ahead reg[3:0] always@(posedgeclkornegedgerst_n){carry_out,sum}<=

{carry_out,sum}=x+Subtractor_4bits //ahead reg[3:0] always@(posedgeclkornegedgerst_n){borrow_out,sub}<=

if(x>=y){borrow_out,sub}={1'b0,x- {borrow_out,sub}={1'b1,x+(~y+{borrow_out,sub}={1'b1,x-FPGA的強大，在并行處理方面的能力，在算法IISimulation給出仿真結果。VerilogHDL硬件描述語言，通過移位以及加法，實現(xiàn)三位二進 [5:0]wire temp0=y[0]?x:wire temp1=y[1]?x:wire temp2=y[2]?x:assignmult_out=temp0+(temp1<<1)+(temp2<<2);assignmult_out=temp0+temp1<<1+temp2<<assignmult_out=temp0+(temp1<<1)+(temp2<<VerilogHDL硬件描述語言，按照要求，設計一個序列檢測器，在檢測4'b1111QuartusII中設計，最后通過QuartusIISimulation給出仿真結果。根據(jù)題目的要求，定義了串行輸入接口：din（X），串行輸出接口dout（Z，同時添加了數(shù)據(jù)輸入標志信號din_en，以指示數(shù)據(jù)的輸入。din_en的高電平信號來檢測輸入信號，因為高電平時間din_en上升沿作為數(shù)據(jù)接受時能標志位。邊沿檢測電路如下RTL所示：串行數(shù)據(jù)輸入序列通過移位操作，存入與sequence_data中，同時檢測sequence_data4'b1111時，dout1表示檢測到了要求的序列。其 din_en,//H regdout//capturetheposedgeofdin_enfordatareceiveregdin_en_r0,din_en_r1;always@(posedgeclkornegedgerst_n)din_en_r0<=din_en_r1<=0;

din_en_r0<=din_en;din_en_r1<=din_en_r0;wiredin_flag=(~din_en_r1&din_en_r0)?1'b1:reg[3:0] always@(posedgeclkornegedgerst_n)sequence_data<=0;dout<=0;sequence_data<={sequence_data[2:0],dout<=(sequence_data==4'b1111)?1'b1:1'b0;1)MCUCPU只能在貸MCU無法勝任的領域，能完美的實現(xiàn)功能。在設計一個計數(shù)器的前提下，要求模值可變，即計數(shù)器最大值可變。因此，wire[7:0]max_vaule=key_index?8'd64:段數(shù)碼管來顯示數(shù)據(jù)。同時為了肉眼能看到數(shù)據(jù)的變化，通過計數(shù)，實現(xiàn)0.2S reg[6:0] =;//---t---=;// =;// =;// =;//---m---=;// =;// =;// =;//---b---=;=;=;=;=;==;;變模計數(shù)模塊串行數(shù)據(jù)輸入序列通過移位操作，存入與sequence_data中，同時檢測sequence_data4'b1111時，dout1( wire max_vaule=key_index?8'd64:reg always@(posedgeclkornegedgerst_n)cnt<=

cnt<=(cnt== )?24'd0:cnt+wiredelay02_flag=(cnt== )?1'b1:1'b0;//0.2s//datareg[7:0] always@(posedgeclkornegedgerst_n)counter<=0;counter<=(counter>=max_vaule)?8'd0:counter+//hex2decimalwire shi_data (counter<10)?(counter<20)? (counter<30)? (counter<40)?4'd3:(counter<50)?4'd4:(counter<60)?4'd5:(counter<70)?4'd6:(counter<80)?4'd7:(counter<90)?4'd8:wire[3:0]ge_data=(counter<10)?counter-(counter<20)?counter-8'd10:(counter<30)?counter-8'd20:(counter<40)?counter-8'd30:(counter<50)?counter-8'd40:(counter<60)?counter-8'd50:(counter<70)?counter-8'd60:(counter<80)?counter-8'd70:(counter<90)?counter-8'd80:counter-8'd90;//shi_datadisy( //ge_datadisy 試驗比較簡單，沒有遇到較大的問題。無非是在個位，十位的提取的時候，不像通過除法器電路趨勢線電路功能，以防在速度上的降低以及資源上的浪費，較笨，但是對于小數(shù)據(jù)而言，已經(jīng)實現(xiàn)了功能。FPGA編程經(jīng)驗，以及多年代碼的積累，很多的模塊都是現(xiàn)成的，最后按照3Sif...else...case語句來實現(xiàn)。但是既實現(xiàn)8個LED的挨個點亮功能，代碼在后面給出。最后通過引腳配置，全局編譯，到DE2-35中，觀察現(xiàn)像，驗證正確， reg reg always@(posedgeclkornegedgerst_n)cnt<=

cnt<=(cnt==28'd150_000000)?28'd0:cnt+wiredelay03_flag=(cnt==28'd150_000000)?1'b1: //3salways@(posedgeclkornegedgerst_n)led_data<=0;led_data<=VerilogHDL的編程能力，涉及的主要內(nèi)容是計數(shù)，其次，并且給分進位，當“分”到達59時候，自動并且給“時”進位（當然本實0-FLab5中已經(jīng)介紹過數(shù)碼管顯示分秒共需要4位數(shù)碼管，而且這在DE2-35電也支持此功能，因此通過最后，全局編譯工程，RTL圖如下所示，time_counter實現(xiàn)了分秒的計數(shù)，通過參數(shù)傳遞給Seg7_lut，實現(xiàn)數(shù)據(jù)在數(shù)碼管上的動態(tài)顯示。下面是可是，4827秒，實驗現(xiàn)象如下所示，47段數(shù)碼管，時刻相當?shù)木珳?，分秒按照常理開始計時，非常的Happy。

reg always@(posedgeclkornegedgerst_n)cnt<=

cnt<=(cnt>=16'd49_999)?16'd0:cnt+wiredelay_1us=(cnt==16'd49_999)?1'b1:1'b0;//1usreg[6:0] reg reg //counterformin,sec,andmsealways@(posedgeclkornegedgerst_n)min<=0;sec<=0;mse<=0;if(min<59)if(sec<59)if(mse<mse<=

mse<=0;sec<=sec+1'b1; if(mse<mse<=mse+1'b1;elsemse<=0;sec<=0;min<=min+1'b1;

if(sec<59)if(mse<mse<=

mse<=0;sec<=sec+1'b1;if(mse<mse<=mse+1'b1;mse<=0;sec<=0;min<=0;

//everybitofminutewire min_h=(min<10)?(min< (min< (min<40)?(min<50)? min_r=(min<10)?min-7'd0(min<20)?min-(min<30)?min-(min<40)?min-(min<50)?min- min_l=min_r[3:0];//everybitofsecondwire sec_h=(sec<10)?(sec< (sec< (sec<40)?(sec<50)? sec_r=(sec<10)?sec-7'd0(sec<20)?sec-(sec<30)?sec-(sec<40)?sec-(sec<50)?sec- sec_l=sec_r[3:0];//everybitofmicrosecondswire[9:0] wire mse_h=(mse< (mse<200)?(mse<(mse<(mse<(mse<(mse<(mse<(mse< mse_br=mse%10'd100/4'd10; mse_lr=mse%4'd10; mse_b=mse_br[3:0]; mse_l= wire wire wire wire[3:0] (min_h), (sec_h), //shi_datadisy ({1'b0, //ge_datadisy //shi_datadisy //ge_datadisy 以前沒在數(shù)碼管上做過時鐘，直接在VGA上面做的，前端設計都一樣，唯一不一樣的是數(shù)碼管電路換成了VGA的字符掃描電路。類似于自己設計一款之后同樣會有20ms左右的抖動。如下圖所示：模擬或者數(shù)字電路中，我們要避免在最不穩(wěn)定的時候信號，進行操作。（2）NN次采樣，來判斷是否改wirecnt_flag= t==20'hffffe)?1'b1:RTLkey_flag按鍵按下反饋信號，以及即時輸出的DE2-3540-9的輸入，因此數(shù)值采用撥個表示X*Y的結果。在《Lab5：變模計數(shù)器設計》中設計到過，根據(jù)要顯示的數(shù)據(jù)，通過不同0-FLab5中已經(jīng)介紹過數(shù)碼管顯示電路，此moduleparameterKEY_WIDTH=)( outputreg[KEY_WIDTH-1:0]//escapethereg //scanreg[KEY_WIDTH-1:0]always@(posedgeclkornegedgerst_n)key_data_r<=t<=key_data_r<= if((key_data==key_data_r)&&(key_data!=//20msescape t<t t+else//if(key_data!=key_data_r||key_data==2'b11)t<=0;wirecnt_flag= t==20'hffffe)?1'b1://surethekeyisregalways@(posedgeclkornegedgerst_n)keyflagr<=0;key_value<=0;elseif(cnt_flag)key_flag_r<=1;key_value<=key_data;//lockedthe //letgoyourkey_flag_r<= //lockthe//Capturetherisingendgeofthekey_flagregkey_flag_r0,key_flag_r1;always@(posedgeclkornegedgerst_n)key_flag_r0<=key_flag_r1<=0;keyflagr0<=keyflagr;key_flag_r1<=key_flag_r0;assignkey_flag=~key_flag_r1&module( keyxflag,//triggerfordata key_yflag,//triggerfordata //triggerfordata //triggerfordata output output output output reg always@(posedgeclkornegedgedin<=

din<= din<= din<= din<= din<= din<= din<= din<= din<= din<= .KEY_WIDTH)( ({key_xfla