FPGA綜合設(shè)計(jì)實(shí)例課件

第十章綜合設(shè)計(jì)實(shí)例第十章綜合設(shè)計(jì)實(shí)例11鍵盤掃描與顯示矩陣式鍵盤:行,列矩陣是鍵盤以行列形式排列，鍵盤上每個(gè)按鍵其實(shí)是一個(gè)開關(guān)電路，當(dāng)某鍵被按下時(shí)，該按鍵對應(yīng)的位置就呈現(xiàn)邏輯0狀態(tài).行掃描方式:逐行送0電平,讀取列的狀態(tài),以判斷按下的鍵號(hào).列掃描方式:逐列送0電平,讀取行的狀態(tài),以判斷按下的鍵號(hào).1鍵盤掃描與顯示矩陣式鍵盤:行,列矩陣是鍵盤以行列形式排列2以行掃描為例:1給行依次送0111,1011,1101,1110信號(hào);2讀取列電平狀態(tài),以行掃描為例:1給行依次送0111,1011,1101,113數(shù)碼管顯示數(shù)碼管顯示4libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitykey_scanisport(column:instd_logic_vector(3downto0);--列狀態(tài)scan_cnt:instd_logic_vector(3downto0);---掃描字row:outstd_logic_vector(3downto0);---行狀態(tài)key_pressed:outstd_logic);-----按鍵有效與否,后續(xù)判斷為零則為有鍵按下end;architecturertlofkey_scanisbeginrow<="1110"whenscan_cnt(3downto2)="00"else"1101"whenscan_cnt(3downto2)="01"else"1011"whenscan_cnt(3downto2)="10"else"0111";key_pressed<=column(0)whenscan_cnt(1downto0)="00"elsecolumn(1)whenscan_cnt(1downto0)="01"elsecolumn(2)whenscan_cnt(1downto0)=“10"elsecolumn(3);endrtl;按鍵掃描控制程序libraryieee;按鍵掃描控制程序5按鍵處理控制模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityscan_countisport(clk:instd_logic;--clockscan_clk:instd_logic;--1khzclkkey_pressed:instd_logic;--檢測按鍵有效與否,停止計(jì)數(shù).scan_cnt:outstd_logic_vector(3downto0));--計(jì)數(shù)end;architecturebehavofscan_countissignalqscan:std_logic_vector(3downto0);beginscan_1:process(clk,scan_clk,key_pressed)beginif(clk'eventandclk='1')thenif(scan_clk='1'andkey_pressed='1')thenqscan<=qscan+1;endif;endif;endprocess;scan_cnt<=qscan;end;按鍵處理控制模塊libraryieee;6按鍵消抖控制模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitydebounceisport(key_pressed:instd_logic;clk:instd_logic;--同步時(shí)鐘scan_clk:instd_logic;--1khzclockkey_valid:outstd_logic);end;architecturebehavofdebounceisbegin

按鍵消抖控制模塊libraryieee;7debounce:process(clk,scan_clk,key_pressed)variabledbnq:std_logic_vector(5downto0);beginif(key_pressed='1')thendbnq:="111111";--unkey_pressed,countresetat63elsif(clk'eventandclk='1')thenifscan_clk='1'thenifdbnq/=1thendbnq:=dbnq-1;--key_pressednotenoughlongtimeendif;endif;endif;ifdbnq=2thenkey_valid<='1';--key_validafterkey_pressed1/63ksecondelsekey_valid<='0';endif;endprocess;end;debounce:process(clk,scan_clk,8鍵盤譯碼及按鍵存儲(chǔ)模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entitycode_tranisport(clk:instd_logic;--clockforsynchronyscan_cnt:instd_logic_vector(3downto0);--1khzclockkey_valid:instd_logic;butt_code:outstd_logic_vector(3downto0));end;architecturebbofcode_tranisbeginprocess(clk)beginif(clk'eventandclk='1')thenifkey_valid='1'thencasescan_cntis鍵盤譯碼及按鍵存儲(chǔ)模塊libraryieee;9when"0000"=>butt_code<="0001";--1when"0001"=>butt_code<="0010";--2when"0010"=>butt_code<="0011";--3when"0011"=>butt_code<="1100";--cwhen"0100"=>butt_code<="0100";--4when"0101"=>butt_code<="0101";--5when"0110"=>butt_code<="0110";--6when"0111"=>butt_code<="1101";--dwhen"1000"=>butt_code<="0111";--7when"1001"=>butt_code<="1000";--8when"1010"=>butt_code<="1001";--9when"1011"=>butt_code<="1110";--ewhen"1100"=>butt_code<="1010";--awhen"1101"=>butt_code<="0000";--0when"1110"=>butt_code<="1011";--bwhenothers=>butt_code<="1111";--fendcase;endif;endif;endprocess;end;when"0000"=>butt_code<="0001";10電鎖控制模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityctrlisport(data_n:instd_logic_vector(3downto0);key_valid,clk:instd_logic;enlock:outstd_logic;d,c,b,a:outstd_logic_vector(3downto0));end;architectureaaaofctrlissignalacc,reg:std_logic_vector(15downto0);signalnc:std_logic_vector(2downto0);signalqa,qb:std_logic;beginkeyin:blockisbegin

process(data_n,key_valid)

電鎖控制模塊libraryieee;11beginifdata_n="1101"thenacc<="0000000000000000";nc<="000";elsifkey_valid'eventandkey_valid='1'thenifdata_n<"1101"thenifnc<=4thenacc<=acc(11downto0)&data_n;nc<=nc+1;endif;endif;endif;endprocess;endblock;lock:blockisbegin

process(clk,data_n)beginif(clk'eventandclk='1')thenifnc=4thenifdata_n="1110"thenreg<=acc;qa<='1';qb<='0';elsifdata_n="1111"thenifreg=accthenqa<='0';qb<='1';endif;endif;endif;endif;endprocess;endblock;begin12enlock<=qaandnotqb;d<=acc(15downto12);c<=acc(11downto8);b<=acc(7downto4);a<=acc(3downto0);endaaa;enlock<=qaandnotqb;13動(dòng)態(tài)掃描顯示控制模塊libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitysel_displayisport(clk:instd_logic;d,c,b,a:instd_logic_vector(3downto0);db_out:outstd_logic_vector(3downto0);dis_out:outstd_logic_vector(3downto0));endentity;architecturertlofsel_displayissignalsel:std_logic_vector(1downto0);signaldis:std_logic_vector(3downto0);signaldb:std_logic_vector(3downto0);begin動(dòng)態(tài)掃描顯示控制模塊libraryieee;14counter:blockissignalq:std_logic_vector(6downto0);beginprocess(clk)beginifclk'eventandclk='1'thenq<=q+1;endif;endprocess;sel<=q(1downto0);endblockcounter;counter:blockis15multiplexer:blockisbeginprocess(sel)beginifsel=0thendb<=d;dis<="0111";elsifsel=1thendb<=c;dis<="1011";elsifsel=2thendb<=b;dis<="1101";elsifsel=3thendb<=a;dis<="1110";endif;endprocess;endblockmultiplexer;db_out<=db;dis_out<=dis;endrtl;multiplexer:blockis16FPGA綜合設(shè)計(jì)實(shí)例ppt課件17FPGA綜合設(shè)計(jì)實(shí)例ppt課件18FPGA綜合設(shè)計(jì)實(shí)例ppt課件19實(shí)例1數(shù)字鐘設(shè)計(jì)實(shí)時(shí)顯示時(shí)、分、秒分析：1、最小計(jì)時(shí)單位：秒。因此，首先要由時(shí)鐘產(chǎn)生1HZ的信號(hào)；2、對秒進(jìn)行0-59的計(jì)數(shù)，并且有進(jìn)位功能，且顯示；3、對分進(jìn)行0-59的計(jì)數(shù)，并且有進(jìn)位功能，且顯示；4、對時(shí)進(jìn)行0-59的計(jì)數(shù)，且顯示；實(shí)例1數(shù)字鐘設(shè)計(jì)實(shí)時(shí)顯示時(shí)、分、秒分析：20FPGA綜合設(shè)計(jì)實(shí)例ppt課件21libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.allentitysecondisport(clk,clr:instd_logic;--clk=1Hzsec1,sec0:outstd_logic_vector(3downto0);co:outstd_logic);endsecond;architecturearchofsecondisbeginprocess(clk,clr)variablecnt1,cnt0:std_logic_vector(3downto0);beginifclr='0'thencnt1:="0000";cnt0:="0000";elsifclk'eventandclk='1'thenifcnt1="0101"andcnt0="1000"thenco<='1';cnt0:="1001";elsifcnt0<"1001"thencnt0:=cnt0+1;elsecnt0:="0000";ifcnt1<"0101"thencnt1:=cnt1+1;elsecnt1:="0000";co<='0';endif;endif;endif;

sec1<=cnt1;sec0<=cnt0;endprocess;endarch;libraryieee;process(clk,clr)22實(shí)例2出租車計(jì)費(fèi)器設(shè)計(jì)功能:（1）實(shí)現(xiàn)計(jì)費(fèi)功能。車起步開始計(jì)費(fèi)，首先顯示起步價(jià)，設(shè)起步費(fèi)為8.00元，車在行駛3km以內(nèi)，只收起步價(jià)8.00元。車行駛超過3km后，每公里2元，車費(fèi)依次累加。當(dāng)總費(fèi)用達(dá)到或超過40元時(shí)，每公里收費(fèi)4元。當(dāng)遇到紅燈或客戶需要停車等待時(shí)，則按時(shí)間計(jì)費(fèi)，計(jì)費(fèi)單價(jià)為每20S收費(fèi)1元。（2）實(shí)現(xiàn)預(yù)置功能：預(yù)置起步費(fèi)、每公里收費(fèi)、車行加費(fèi)里程、計(jì)時(shí)收費(fèi)。（3）實(shí)現(xiàn)模擬功能：模擬汽車行駛、停止、暫停等狀態(tài)。（4）實(shí)現(xiàn)顯示功能：將路程與車費(fèi)顯示出來，以十進(jìn)制顯示。實(shí)例2出租車計(jì)費(fèi)器設(shè)計(jì)功能:23模塊speed模塊kmmoney判斷總費(fèi)用kmmoney判斷行駛里程kmcount模塊kilometers模塊timeresetstartsp模塊speed模塊判斷總費(fèi)用判斷行駛里程模塊模塊timer24系統(tǒng)流程如下：

（1）系統(tǒng)接收到reset信號(hào)后，總費(fèi)用變?yōu)?元，同時(shí)其他計(jì)數(shù)器，寄存器等全部清零。

（2）系統(tǒng)接收到start信號(hào)后，首先把部分寄存器賦值，總費(fèi)用不變，單價(jià)price寄存器通過對總費(fèi)用的判斷后賦為2元。其他寄存器和計(jì)數(shù)器等繼續(xù)保持為0。

（3）speed進(jìn)程：通過對速度信號(hào)sp的判斷，決定變量kinside的值。kinside即是行進(jìn)100m所需要的時(shí)鐘周期數(shù)，然后每行進(jìn)100m，則產(chǎn)生一個(gè)脈沖clkout。

（4）kilometers進(jìn)程：由于一個(gè)clkout信號(hào)代表行進(jìn)100m，故通過對clkout計(jì)數(shù)，可以獲得共行進(jìn)的距離kmcount。

（5）time進(jìn)程：在汽車啟動(dòng)后，當(dāng)遇到顧客等人或紅燈時(shí)，出租車采用計(jì)時(shí)收費(fèi)的方式。通過對速度信號(hào)sp的判斷決定是否開始記錄時(shí)間。當(dāng)sp=0時(shí)，開始記錄時(shí)間。當(dāng)時(shí)間達(dá)到足夠長時(shí)則產(chǎn)生timecount脈沖，并重新計(jì)時(shí)。一個(gè)timecount脈沖相當(dāng)于等待的時(shí)間達(dá)到了時(shí)間計(jì)費(fèi)的長度。這里選擇系統(tǒng)時(shí)鐘頻率為500Hz，20s即計(jì)數(shù)值為1000。

（6）kmmoney可分為kmmoney1和kmmoney2兩個(gè)進(jìn)程。

kmmoney1進(jìn)程：根據(jù)條件對enable和price賦值。當(dāng)記錄的距離達(dá)到3公里后enable變?yōu)椤?’，開始進(jìn)行每公里收費(fèi)，當(dāng)總費(fèi)用大于40元后，則單價(jià)price由原來的2元每公里變?yōu)?元每公里。

kmmoney2進(jìn)程：在每個(gè)時(shí)鐘周期判斷timecount和clkout的值。當(dāng)其為‘1’時(shí)，則在總費(fèi)用上加上相應(yīng)的費(fèi)用。系統(tǒng)流程如下：（1）系統(tǒng)接收到reset信號(hào)后，總費(fèi)用變?yōu)?5FPGA綜合設(shè)計(jì)實(shí)例ppt課件26speed模塊speed進(jìn)程首先根據(jù)start信號(hào)判斷是否開始計(jì)費(fèi)，然后根據(jù)輸入的速度檔位sp[2..0]的判斷，確定行駛100M所需要的時(shí)鐘數(shù)，每前進(jìn)100M，輸出一個(gè)clkout信號(hào)。同時(shí)由cnt對clk進(jìn)行計(jì)數(shù)，當(dāng)cnt=kinside時(shí)，把clkout信號(hào)置‘1’，cnt清0。speed模塊27Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntityfeesystemisPort(clk:instd_logic;reset:instd_logic;start:instd_logic;stop:instd_logic;sp:instd_logic_vector(2downto0);clkout:outstd_logic);endfeesystem;architecturebehavoffeesystemisbeginprocess(clk,reset,stop,start,sp)typestate_typeis(s0,s1);variables_state:state_type;variablecnt:integerrange0to28;variablekinside:integerrange0to30;begincasespis---7檔速度選擇，具體每檔kinside的值可根據(jù)實(shí)際情況設(shè)定when"000"=>kinside:=0;--停止?fàn)顟B(tài)或空擋Libraryieee;28when"001"=>kinside:=28;--第一檔，慢速行駛狀態(tài)，行駛100m需要28個(gè)時(shí)鐘周期when"010"=>kinside:=24;--第二檔 when"011"=>kinside:=20;--第三檔when"100"=>kinside:=16;--第四檔when"101"=>kinside:=12;--第五檔when"110"=>kinside:=8;--第六檔when"111"=>kinside:=4;--第七檔，也是速度最大的檔endcase;ifreset='1'thens_state:=s0;elsifclk'eventandclk='1'thencases_stateiswhens0=>cnt:=0;clkout<='0';ifstart='1'thens_state:=s1;elses_state:=s0;endif;

when"001"=>kinside:=28;--第29whens1=>clkout<='0';ifstop='1'thens_state:=s0;--相當(dāng)于無客戶上車elsifsp="000"thens_state:=s1;---有客戶上車，但車速位0，即客戶剛上車還未起步elsifcnt=kinsidethencnt:=0;clkout<='1';s_state:=s1;elsecnt:=cnt+1;s_state:=s1;endif;endcase;endif;endprocess;endbehav;whens1=>30kilometers模塊此模塊主要用于記錄行進(jìn)的距離。通過對clkout信號(hào)的計(jì)數(shù)，可以計(jì)算行駛的距離kmcount。一個(gè)clkout脈沖相當(dāng)于行進(jìn)100m，所以只要記錄clkout的脈沖數(shù)目即可確定共行進(jìn)的距離。kmcount1為十分位，kmcount2為個(gè)位,kmcount3為十位，分別為十進(jìn)制數(shù)。kilometers模塊31Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitykilometersisPort(clkout,reset:instd_logic;kmcnt1:outstd_logic_vector(3downto0);kmcnt2:outstd_logic_vector(3downto0);kmcnt3:outstd_logic_vector(3downto0));endkilometers;architecturebehavofkilometersisbeginprocess(clkout,reset)variablekm_reg:std_logic_vector(11downto0);beginifreset='1'thenkm_reg:="000000000000";elsifclkout'eventandclkout='1'then--km_reg(3downto0)對應(yīng)里程十分位Libraryieee;32ifkm_reg(3downto0)="1001"thenkm_reg:=km_reg+"0111";--十分位向個(gè)位的進(jìn)位處理elsekm_reg(3downto0):=km_reg(3downto0)+"0001";endif;ifkm_reg(7downto4)="1010"thenkm_reg:=km_reg+"01100000";--個(gè)位向十位的進(jìn)位處理endif;endif;kmcnt1<=km_reg(3downto0);kmcnt2<=km_reg(7downto4);kmcnt3<=km_reg(11downto8);endprocess;endbehav;ifkm_reg(3downto0)="1001"t33time模塊time模塊主要用于計(jì)時(shí)收費(fèi)。記錄計(jì)程車速度為0的時(shí)間（如等待紅燈）。通過對sp信號(hào)的判斷，當(dāng)sp=0，開始記錄時(shí)間。當(dāng)時(shí)間達(dá)到足夠長時(shí)，產(chǎn)生timecount脈沖，并重新計(jì)時(shí)。time進(jìn)程，產(chǎn)生時(shí)間計(jì)費(fèi)脈沖timecount，單位計(jì)費(fèi)時(shí)間可設(shè)定，這里選為20stime模塊34Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitytimeisPort(clk,reset,start,stop:instd_logic;Sp:instd_logic_vector(2downto0);Timecount:outstd_logic);Endtime;architecturebehavoftimeisbeginprocess(reset,clk,sp,stop,start)typestate_typeis(t0,t1,t2);variablet_state:state_type;variablewaittime:integerrange0to1000;beginifreset='1'thent_state:=t0;elsif(clk'eventandclk='1')thenLibraryieee;35caset_stateiswhent0=>waittime:=0;timecount<='0';ifstart='1'thent_state:=t1;elset_state:=t0;endif;whent1=>ifsp="000"thent_state:=t2;elsewaittime:=0;t_state:=t1;endif;whent2=>waittime:=waittime+1;timecount<='0';ifwaittime=1000thentimecount<='1';--20s,即1000個(gè)clk，產(chǎn)生一個(gè)時(shí)間計(jì)費(fèi)脈沖waittime:=0;elsifstop='1'thent_state:=t0;elsifsp="000"thent_state:=t2;elsetimecount<='0';t_state:=t1;endif;endcase;endif;endprocess;endbehav;caset_stateis36kmmoney模塊kmmoney可分為kmmoney1和kmmoney2兩個(gè)模塊。

kmmoney1用于產(chǎn)生enable和price信號(hào)。當(dāng)記錄距離達(dá)到3公里后，enable信號(hào)為‘1’，開始進(jìn)行每公里的收費(fèi)。當(dāng)總費(fèi)用大于40元后，單價(jià)price由原來的2元變?yōu)?元。用作計(jì)時(shí)收費(fèi)。通過對sp信號(hào)的判斷，當(dāng)sp=0，開始記錄時(shí)間。當(dāng)時(shí)間達(dá)到足夠長時(shí)，產(chǎn)生timecount脈沖，并重新計(jì)時(shí)。kmmoney2用于判斷timecount和clkout的值，當(dāng)其為‘1’時(shí)，總費(fèi)用加1。最終輸出為總費(fèi)用。計(jì)費(fèi)采用兩個(gè)進(jìn)程kmmoney1和kmmoney2實(shí)現(xiàn);總費(fèi)用上限位999元，一旦超過上限，顯示會(huì)出現(xiàn)不正常現(xiàn)象kmmoney模塊計(jì)費(fèi)采用兩個(gè)進(jìn)程kmmoney1和kmmo37Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;EntitykmmoneyisPort(clk,reset,timecount,clkout:instd_logic;Kmcnt2:instd_logic_vector(3downto0);Kmcnt3:instd_logic_vector(3downto0);Count1:outstd_logic_vector(3downto0);Count2:outstd_logic_vector(3downto0);Count3:outstd_logic_vector(3downto0));Endkmmoney;ArchitecturebehavofkmmoneyisSignalcash:std_logic_vector(11downto0);Signalprice:std_logic_vector(3downto0);Signalenable:std_logic;BeginProcess(cash,kmcnt2)BeginIfcash>="000001000000"thenprice<="0100";Elseprice<="0010";Endif;Libraryieee;38If(kmcnt2>="0011")or(kmcnt3>="0001")thenenable<='1';Elseenable<='0';Endif;Endprocess;kmmoney2:process(reset,clkout,clk,enable,price,kmcnt2)variablereg2:std_logic_vector(11downto0);variableclkout_cnt:integerrange0to10;beginifreset='1'thencash<="000000001000";--起步費(fèi)用設(shè)為8元elsifclk'eventandclk='1'theniftimecount='1'then--判斷是否需要時(shí)間計(jì)費(fèi)，每20s加一元reg2:=cash;ifreg2(3downto0)+"0001">"1001"thenreg2(7downto0):=reg2(7downto0)+"00000111";ifreg2(7downto4)>"1001"thencash<=reg2+"000001100000";elsecash<=reg2;endif;elsecash<=reg2+"0001";endif;elsifclkout='1'andenable='1'then--里程計(jì)費(fèi)If(kmcnt2>="0011")or(kmcnt3>=39ifclkout_cnt=9thenclkout_cnt:=0;reg2:=cash;if"0000"®2(3downto0)+price(3downto0)>"00001001"thenreg2(7downto0):=reg2(7downto0)+"00000110"+price;ifreg2(7downto4)>"1001"thencash<=reg2+"000001100000";elsecash<=reg2;endif;elsecash<=reg2+price;endif;elseclkout_cnt:=clkout_cnt+1;endif;endif;endif;endprocess;count1<=cash(3downto0);--總費(fèi)用的個(gè)位count2<=cash(7downto4);--總費(fèi)用的十位count3<=cash(11downto8);--總費(fèi)用的百位Endbehav;ifclkout_cnt=9then40FPGA綜合設(shè)計(jì)實(shí)例ppt課件41分頻模塊對系統(tǒng)的時(shí)鐘進(jìn)行分頻，以模擬輪胎的滾動(dòng)。（a）100分頻(b)10分頻分頻模塊42Libraryieee;Useieee.std_logic_1164.all;entityfpisport(clr,clk:instd_logic;newclk:outstd_logic);endfp;architecturebehavoffpissignaltem:integerrange0to99;beginprocess(clk,clr)beginif(clr='1')thentem<=0;newclk<='0';elsif(clk'eventandclk='1')thenif(tem=99)thentem<=0;newclk<='1';elsetem<=tem+1;newclk<='0';endif;endif;endprocess;endbehav;Libraryieee;43Libraryieee;Useieee.std_logic_1164.all;entityfp10isport(clr,clk:instd_logic;newclk:outstd_logic);endfp10;architecturebehavoffp10issignaltem:integerrange0to9;beginprocess(clk,clr)beginif(clr='1')thentem<=0;newclk<='0';elsif(clk'eventandclk='1')thenif(tem=9)thentem<=0;newclk<='1';elsetem<=tem+1;newclk<='0';endif;endif;endprocess;endbehav;Libraryieee;44顯示模塊顯示模塊45libraryieee;useieee.std_logic_1164.all;entitysev_yimaisport(s:instd_logic_vector(3downto0);q:outstd_logic_vector(6downto0));endsev_yima;architecturertlofsev_yimaisbeginwithsselectq<="1000000"when"0000","1111001"when"0001","0100100"when"0010","0110000"when"0011","0011001"when"0100","0010010"when"0101","0000010"when"0110","1111000"when"0111","0000000"when"1000","0010000"when"1001","1111111"whenothers;endrtl;libraryieee;46實(shí)例3頻率計(jì)設(shè)計(jì)要求：對輸入信號(hào)進(jìn)行頻率的測量并實(shí)時(shí)顯示。實(shí)例3頻率計(jì)設(shè)計(jì)要求：對輸入信號(hào)進(jìn)行頻率的測量并實(shí)時(shí)顯示47

分頻器模塊時(shí)鐘信號(hào)源輸出的時(shí)鐘信號(hào)頻率高達(dá)50MHz,經(jīng)過分頻器將其分頻為1Hz、4Hz、500Hz和1000Hz時(shí)鐘信號(hào)。這四種信號(hào)再經(jīng)過1/2分頻,得到時(shí)間基準(zhǔn)信號(hào),其中1000Hz的時(shí)鐘基準(zhǔn)信號(hào)用于動(dòng)態(tài)掃描譯碼電路,1Hz的時(shí)鐘基準(zhǔn)信號(hào)用于計(jì)數(shù)器的始能信號(hào)。分頻器模塊48libraryieee;useieee.std_logic_1164.all;entityfenpinisport(clk:instd_logic;--50MHzclk1:outstd_logic;--1Hzclk2:outstd_logic;--4Hzclk3:outstd_logic;--500hzclk4:outstd_logic--1khz);endfenpin;architecturearchoffenpinisbeginprocess(clk)variablecnt1:integerrange0to49999999;variablecnt2:integerrange0to12499999;variablecnt3:integerrange0to99999;variablecnt4:integerrange0to49999;variablex1,x2,x3,x4:std_logic:='0';beginifclk'eventandclk='1'thenifcnt1<49999999thencnt1:=cnt1+1;elsecnt1:=0;x1:=notx1;endif;ifcnt2<12499999thencnt2:=cnt2+1;elsecnt2:=0;x2:=notx2;endif;ifcnt2<99999thencnt3:=cnt3+1;elsecnt3:=0;x3:=notx3;endif;ifcnt4<49999thencnt4:=cnt4+1;elsecnt4:=0;x4:=notx4;endif;endif;clk1<=x1;clk2<=x2;clk3<=x3;clk4<=x4;endprocess;endarch;libraryieee;cnt1:=cnt1+1;49

計(jì)數(shù)器模塊計(jì)數(shù)器模塊始能端door輸入分頻器模塊分頻出的0.5Hz為基準(zhǔn)時(shí)鐘信號(hào)頻率。計(jì)數(shù)器sig輸入待測信號(hào)與基準(zhǔn)時(shí)鐘信號(hào)進(jìn)行比較，并且計(jì)數(shù)。q0[3..0]對應(yīng)的是個(gè)位輸出，q1[3..0]對應(yīng)的是十位輸出，q2[3..0]對應(yīng)的是百位輸出，q3[3..0]對應(yīng)的是千位輸出。計(jì)數(shù)器模塊50libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitymeasureisport(sig,door:instd_logic;q3,q2,q1,q0,dang:outstd_logic_vector(3downto0));endmeasure;architecturearchofmeasureissignalc0,c1,c2,c3,c4,c5,c6:std_logic_vector(3downto0):="0000";signalsuo:std_logic;--lockthecountnumberbeginprocess(door,sig)beginlibraryieee;51ifsig'eventandsig='1'thenifdoor='1'thensuo<='1';ifc0<"1001"thenc0<=c0+1;elsec0<="0000";ifc1<"1001"thenc1<=c1+1;elsec1<="0000";ifc2<"1001"thenc2<=c2+1;elsec2<="0000";ifc3<"1001"thenc3<=c3+1;elsec3<="0000";ifc4<"1001"thenc4<=c4+1;elsec4<="0000";ifc5<"1001"thenc5<=c5+1;elsec5<="0000";ifc6<"1001"thenc6<=c6+1;elseifsig'eventandsig='1'then52c6<="0000";endif;endif;endif;endif;endif;endif;endif;else--toifdoor='1'c0<="0000";c1<="0000";c2<="0000";c3<="0000";c4<="0000";c5<="0000";c6<="0000";suo<='0';ifsuo='1'thenifc6/="0000"thenq3<=c6;q2<=c5;q1<=c4;q0<=c3;dang<="0100";elsifc5/="0000"thenq3<=c5;q2<=c4;q1<=c3;q0<=c2;dang<="0010";elsifc4/="0000"thenq3<=c4;q2<=c3;q1<=c2;q0<=c1;dang<="0010";elseq3<=c3;q2<=c2;q1<=c1;q0<=c0;dang<="0001";endif;elsenull;endif;endif;--toifdoor='1'elsenull;--toifsig'eventandsig='1'thenendif;endprocess;endarch;c6<="0000";q3<=c6;q2<=c5;q1<53鎖存器模塊鎖存器模塊主要由1個(gè)鎖存器組成,主要作用是鎖存計(jì)數(shù)器的計(jì)數(shù)值。設(shè)置鎖存器可以使數(shù)據(jù)顯示穩(wěn)定可靠,不會(huì)由于周期性的清零信號(hào)而使數(shù)碼管不斷閃爍。鎖存信號(hào)由控制電路產(chǎn)生,在1個(gè)周期的計(jì)數(shù)時(shí)間結(jié)束時(shí),鎖存器立即鎖存計(jì)數(shù)值。鎖存器的數(shù)據(jù)輸入端與計(jì)數(shù)器數(shù)據(jù)輸出端連接,數(shù)據(jù)輸出與動(dòng)態(tài)掃描譯碼電路中的顯示譯碼電路連接,時(shí)鐘輸入端與基準(zhǔn)時(shí)鐘電路端連接。在信號(hào)的上升沿,將計(jì)數(shù)器中的測量數(shù)據(jù)存入鎖存器。a2[3..0]對應(yīng)的是個(gè)位輸入，a3[3..0]對應(yīng)的是十位輸入，a4[3..0]對應(yīng)的是百位輸入，a5[3..0]對應(yīng)的是千位輸入，q2[3..0]對應(yīng)的是個(gè)位輸出，q3[3..0]對應(yīng)的是十位輸出，q4[3..0]對應(yīng)的是百位輸出，q5[3..0]對應(yīng)的是千位輸出鎖存，clk連接的是分頻器分頻出的1000HZ的信號(hào)。鎖存器模塊a2[3..0]對應(yīng)的是個(gè)位輸入，a3[3..0]54libraryieee;useieee.std_logic_1164.all;entitylockisport(clk:instd_logic;a5,a4,a3,a2,a1,a0:instd_logic_vector(3downto0);q5,q4,q3,q2,q1,q0:outstd_logic_vector(3downto0));endlock;architecturearchoflockissignalaa5,aa4,aa3,aa2,aa1,aa0:std_logic_vector(3downto0);beginprocess(clk)beginifclk'eventandclk='0'thenaa5<=a5;aa4<=a4;aa3<=a3;aa2<=a2;aa1<=a1;aa0<=a0;endif;q5<=aa5;q4<=aa4;q3<=aa3;q2<=aa2;q1<=aa1;q0<=aa0;endprocess;endarch;libraryieee;55譯碼器模塊譯碼器模塊主要由4個(gè)顯示模塊組成。主要功能是將鎖存器保存的4位二進(jìn)制計(jì)數(shù)值轉(zhuǎn)換成相應(yīng)的數(shù)碼管顯示代碼,顯示模塊輸出端與4個(gè)7段數(shù)碼管相連,可以在數(shù)碼管上顯示所測頻率的十進(jìn)制輸出值。d[3..0]對應(yīng)的是譯碼信號(hào)的輸入，q[6..0]對應(yīng)的是譯碼信號(hào)的輸出。譯碼器模塊56FPGA綜合設(shè)計(jì)實(shí)例ppt課件57FPGA綜合設(shè)計(jì)實(shí)例ppt課件58FPGA綜合設(shè)計(jì)實(shí)例ppt課件59實(shí)例4交通燈模擬系統(tǒng)設(shè)計(jì)結(jié)合DEII實(shí)際，擬用不同顏色發(fā)光二極管模擬南北方向和東西方向的紅綠燈；每個(gè)方向有紅、綠、黃三個(gè)燈，并能對綠燈放行時(shí)間進(jìn)行設(shè)置和調(diào)整。實(shí)例4交通燈模擬系統(tǒng)設(shè)計(jì)結(jié)合DEII實(shí)際，擬用不同顏色發(fā)光60控制模塊設(shè)計(jì)本模塊主要實(shí)現(xiàn)對兩個(gè)方向紅綠燈的交替顯示控制。其中Clock是時(shí)鐘源，為分頻模塊的輸出信號(hào)；hold是控制信號(hào)，起保持功能;countnum是計(jì)數(shù)模塊的輸出信號(hào)，為一個(gè)周期的循環(huán)計(jì)數(shù)值；numa是a組交通燈輸出；numb是b組交通燈輸出;reda是a組紅燈輸出；greenda是a組綠燈輸出；yellowa是a組黃燈輸出；redb是b組紅燈輸出；greendb是b組綠燈輸出；yellowb是a組黃燈輸出；flash是閃爍輸出控制模塊設(shè)計(jì)其中Clock是時(shí)鐘源，為分頻模塊的輸出信號(hào)；h61libraryieee;useieee.std_logic_1164.all;entitycontrollerisport(clock:instd_logic;hold:instd_logic;countnum:inintegerrange0to49;numa,numb:outintegerrange0to25;reda,greena,yellowa:outstd_logic;redb,greenb,yellowb:outstd_logic;flash:outstd_logic);endcontroller;architecturearchofcontrollerisbeginprocess(clock)beginiffalling_edge(clock)thenifhold='0'thenreda<='0';redb<='0';greena<='1';greenb<='1';yellowa<='1';yellowb<='1';flash<='1';elseflash<='0';------------------------------------------------ifcountnum<=19thennuma<=20-countnum;reda<='1';greena<='0';yellowa<='1';elsifcountnum<=24then

numa<=25-countnum;reda<='1';greena<='1';yellowa<='0';elsenuma<=50-countnum;reda<='0';greena<='1';yellowa<='1';endif;libraryieee;reda<='0';62------------------------------------------------ifcountnum<=24thennumb<=25-countnum;redb<='0';greenb<='1';yellowb<='1';elsifcountnum<=44thennumb<=45-countnum;redb<='1';greenb<='0';yellowb<='1';elsenumb<=50-countnum;redb<='1';greenb<='1';yellowb<='0';endif;

endif;endif;endprocess;endarch;------------------------------63計(jì)數(shù)模塊設(shè)計(jì)本模塊主要實(shí)現(xiàn)一個(gè)周期的循環(huán)計(jì)數(shù)，在此以50秒為一個(gè)周期進(jìn)行循環(huán)計(jì)數(shù)，當(dāng)然可以根據(jù)實(shí)際情況進(jìn)行調(diào)整，如調(diào)整為60秒或120秒。0-50的計(jì)數(shù)范圍用二進(jìn)制表示則需要六位，因此本模塊的計(jì)數(shù)輸出為六位，如果需要調(diào)整計(jì)數(shù)周期，則計(jì)數(shù)的輸出位數(shù)需要相應(yīng)調(diào)整。計(jì)數(shù)模塊設(shè)計(jì)64libraryieee;useieee.std_logic_1164.all;entitycounterisport(clock:instd_logic;reset:instd_logic;hold:instd_logic;countnum:bufferintegerrange0to49);endcounter;architecturearchofcounterisbeginprocess(reset,clock)beginifreset='0'thencountnum<=0;elsifrising_edge(clock)thenifhold='0'thencountnum<=countnum;elseifcountnum=49thencountnum<=0;elsecountnum<=countnum+1;endif;endif;endif;endprocess;endarch;libraryieee;65分位模塊設(shè)計(jì)由于十字路口的倒計(jì)時(shí)范圍為：0-25，因此顯示的時(shí)候需要兩個(gè)LED數(shù)碼管，本模塊是將計(jì)數(shù)值由二進(jìn)制轉(zhuǎn)換為十進(jìn)制，并分成十位和個(gè)位。圖中num1是十位輸出，num2是個(gè)位輸出，numin是輸入的二進(jìn)制數(shù)，由于輸入的數(shù)據(jù)為0-25，因此五位二進(jìn)制數(shù)即可滿足條件。分位模塊設(shè)計(jì)66libraryieee;useieee.std_logic_1164.all;entityfenweiisport(numin:inintegerrange0to25;num1,num2:outintegerrange0to9);endfenwei;architecturearchoffenweiisbeginprocess(numin)beginifnumin>=20thennum1<=2;num2<=numin-20;elsifnumin>=10thennum1<=1;num2<=numin-10;elsenum1<=0;num2<=numin;endif;endprocess;endarch;libraryieee;67顯示模塊設(shè)計(jì)本模塊的功能是將兩個(gè)方向的倒計(jì)時(shí)數(shù)值進(jìn)行顯示。顯示模塊設(shè)計(jì)68FPGA綜合設(shè)計(jì)實(shí)例ppt課件69基于FPGA的紅外遙控器設(shè)計(jì)紅外線遙控系統(tǒng)就是指利用紅外線來傳遞控制信號(hào)，從而實(shí)現(xiàn)對控制對象的遠(yuǎn)距離控制。具體來講，就是由發(fā)射器發(fā)出紅外線指令信號(hào)，由接受器接受信號(hào)并對信號(hào)進(jìn)行處理，最后實(shí)現(xiàn)對對象的各種功能的遠(yuǎn)距離控制。紅外線遙控系統(tǒng)一般由發(fā)射器和接受器兩部分組成。發(fā)射器：指令鍵、指令信號(hào)產(chǎn)生電路、調(diào)制電路、驅(qū)動(dòng)電路及紅外線發(fā)射器件。接受器：紅外線接受器件、前置放大電