計(jì)算機(jī)組成與結(jié)構(gòu)

ECE313Fall2006Lecture20-Memory1/89Roadmapfortheterm:majortopicsOverview/AbstractionsandTechnologyInstructionsetsLogic&arithmeticPerformanceProcessorImplementationSingle-cycleimplemenatationMulticycleimplementationPipelinedImplementationMemorysystems 3Input/Output

ECE313Fall2006Lecture20-Memory2/89Outline-MemorySystemsOverview 3MotivationGeneralStructureandTerminology(術(shù)語)MemoryTechnologyStaticRAMDynamicRAMDisksCacheMemoryVirtualMemoryECE313Fall2006Lecture20-Memory3/89MemorySystems-theBigPictureMemoryprovidesprocessorwithInstructionsDataProblem:memoryistooslowandtoosmallControlDatapathMemoryProcessorInputOutputInstructionsData“FiveClassicsComponents”PictureECE313Fall2006Lecture20-Memory4/89MemoryHierarchy-theBigPictureProblem:memoryistooslowandtoosmallSolution:memoryhierarchy（層次）-分層存儲器FastestSlowestSmallestBiggestHighestLowestSpeed:Size:Cost:ControlDatapathSecondaryStorage(Disk)ProcessorRegistersL2Off-ChipCacheMainMemory(DRAM)L1On-ChipCacheECE313Fall2006Lecture20-Memory5/89WhyHierarchyWorksTheprincipleoflocality（局部性原理）Programsaccessarelativelysmallportionoftheaddressspaceatanyinstantoftime.-在任一瞬間，程序只訪問地址空間中的一小部分

Temporallocality:recentlyaccesseddataislikelytobeusedagainSpatiallocality:datanearrecentlyaccesseddataislikelytobeusedsoonResult:theillusion(幻想)oflarge,fastmemoryAddressSpace02n-1ProbabilityofreferenceECE313Fall2006Lecture20-Memory6/89MemoryHierarchy-Speedvs.SizeControlDatapathSecondaryStorage(Disk)ProcessorRegistersL2Off-ChipCacheMainMemory(DRAM)L1On-ChipCache0.5-255,000,000(5ms)Speed(ns):80-250<1KSize(bytes):>100G<16G<16M0.25-0.5ECE313Fall2006Lecture20-Memory7/89MemoryHierarchy–Terminology術(shù)語ProcessorBlocksofDataHit:DatainUpperLevelMiss:DatanotinUpperLevel數(shù)據(jù)復(fù)制每次只在兩個(gè)相鄰層次間進(jìn)行ECE313Fall2006Lecture20-Memory8/89存儲器層次結(jié)構(gòu)的幾個(gè)術(shù)語Hit:處理器需要的數(shù)據(jù)出現(xiàn)在高層的某個(gè)塊中(greenblock)HitRate:thefractionofmemoryaccessesthat“hit”HitTime:timetoaccesstheupperlevel

(timetodeterminehit/miss+accesstime)Miss:datamustberetrievedfromblockinlowerlevel(orangeblock)缺失率MissRate=1-(HitRate)MissPenalty:Timetoreplaceblockinupperlevel+TimetodeliverdatatotheprocessorHitTime<<MissPenaltyandHitRate>>MissRateECE313Fall2006Lecture20-Memory9/89TypicalMemoryHierarchy-DetailsRegisters-Small,fasteston-chipstorageManagedbycompilerandrun-timesystemCache-Small,faston-chipstorageAssociativelookup-managedbyhardwareMemory-Slower,Largeroff-chipstorageLimitedsize<16Gb-managedbyhardware,OSDisk-Slowest,Largestoff-chipstorageVirtualmemory–simulatealargememoryusingdisk,hardware,andoperatingsystemFilestorage-storedatafilesusingoperatingsystemECE313Fall2006Lecture20-Memory10/89存儲器系統(tǒng)影響計(jì)算機(jī)的許多方面用于構(gòu)造存儲器系統(tǒng)的概念影響到計(jì)算機(jī)的許多方面，如：OS對存儲器和I/O如何管理編譯器如何生成代碼應(yīng)用程序如何使用計(jì)算機(jī)性能評估因而，設(shè)計(jì)人員花費(fèi)了相當(dāng)?shù)木﹂_發(fā)復(fù)雜的機(jī)制以提高存儲器系統(tǒng)的性能本章進(jìn)行了大量抽象和簡化ECE313Fall2006Lecture20-Memory11/89Outline-MemorySystemsOverview MotivationGeneralStructureandTerminologyMemoryTechnology 3StaticRAM DynamicRAMCacheMemoryVirtualMemoryECE313Fall2006Lecture20-Memory12/89MemoryTypesStaticRAMStorageusinglatchcircuits(門鎖電路）Valuessavedwhilepoweron

DynamicRAMStorageusingcapacitors（電容）Valuesmustberefreshedbitbitword/rowselect1001word/rowselectbitCECE313Fall2006Lecture20-Memory13/89Tradeoffs-Staticvs.DynamicRAMStaticRAM(SRAM)-usedforL1,L2cacheFast-0.5-25nsaccesstime(lessforon-chip)Larger,MoreExpensiveHigherpowerconsumptionDynamicRAM(DRAM)-usedforPCmainmemorySlower-80-250nsaccesstime*Smaller,CheaperLowerpowerconsumptionECE313Fall2006Lecture20-Memory14/89DRAMOrganizationRowDecoderColumnSelector/Latch/IORowAddressColumnAddress/RAS/CASDATARowSelectLineBit(data)LineECE313Fall2006Lecture20-Memory15/8900010011DRAMReadOperationRowDecoderColumnSelector/Latch/IORowAddressColumnAddress/RAS/CASDATAECE313Fall2006Lecture20-Memory16/89DRAMTrends（趨勢）RAMsize:4Xevery3yearsRAMspeed:2Xevery10years

DRAMYear Size CycleTime1980 64Kb 250ns1983 256Kb 220ns1986 1Mb 190ns1989 4Mb 165ns1992 16Mb 145ns1995 64Mb 120ns1997? 128Mb ??ns1999? 256Mb ??ns1980-1995Sizechange:

1000:1!1980-1995Speedchange:

2:1!ECE313Fall2006Lecture20-Memory17/89TheProcessor/MemorySpeedGapDRAM9%/yr.(2X/10yrs)110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformanceGap:

(grows50%/year)PerformanceTime“Moore’sLaw”ECE313Fall2006Lecture20-Memory18/89定位導(dǎo)致速度差異的原因

AddressingtheSpeedGapLatencydependsonphysicallimitationsBandwidthcanbeincreasedusing:并行Parallelism–transfer(傳輸)morebits/wordBursttransfers-transfersuccessivewordsoneachcycle在每個(gè)周期中傳輸連續(xù)的機(jī)器字So...usebandwidthtosupportmemoryhierarchy(層次)!UsecachetosupportlocalityofreferenceDesignhierarchytotransferlarge

blocksofmemoryECE313Fall2006Lecture20-Memory19/89CurrentDRAMPartsSynchronous同步的DRAM(SDRAM)-clockedtransferofburstsofdatastartingataspecificaddressDouble-DataRateSDRAM-transfertwobits/clockcycleQuad（方形）-DataRateSDRAM-transferfourbits/clockcycleRambusRDRAM-High-speedinterfaceforfasttransfersCurrentPCsusesomeformofSDRAM/RDRAMSDRAMw/PC100orPC133memorybusRDRAMw/PC800memorybusECE313Fall2006Lecture20-Memory20/89MemoryConfigurationinCurrentPCsProcessorSystemControllerL1CacheMainMemory(DRAM)L2/L3Cache(SRAM)(I/OBus)ECE313Fall2006Lecture20-Memory21/89主存是以存儲芯片為基本單位構(gòu)成用16K×1位的存儲芯片組成64K×8位的存儲器

32片當(dāng)?shù)刂窞?5535時(shí)，此8片的片選有效8片16K×1位8片16K×1位8片16K×1位8片16K×1位ECE313Fall2006Lecture20-Memory22/890,015,015,70,7

讀/寫控制電路

地址譯碼器

字線015…………16×8矩陣…………07D07D位線讀/寫選通A3A2A1A0……存儲芯片的譯碼驅(qū)動(dòng)方式-線選法00000,00,7…0……07……D07D讀/寫選通ECE313Fall2006Lecture20-Memory23/89A3A2A1A0A40,310,031,031,31

Y地址譯碼器

X地址譯碼器

32×32矩陣……A9I/OA8A7A56AY0Y31X0X31D讀/寫……存儲芯片的譯碼驅(qū)動(dòng)方式-重合法00000000000,031,00,31……I/OD0,0讀ECE313Fall2006Lecture20-Memory24/89靜態(tài)RAM(SRAM)基本電路A′觸發(fā)器非端1T4T~觸發(fā)器5TT6、行開關(guān)7TT8、列開關(guān)7TT8、一列共用A

觸發(fā)器原端T1~T4T5T6T7T8A′A寫放大器寫放大器DIN寫選擇讀選擇DOUT讀放位線A位線A′列地址選擇行地址選擇T1~T4ECE313Fall2006Lecture20-Memory25/89A′T1

~T4T5T6T7T8A寫放大器寫放大器DIN寫選擇讀選擇讀放位線A位線A′列地址選擇行地址選擇DOUT靜態(tài)RAM基本電路的讀

操作行選

T5、T6開T7、T8開列選讀放DOUTVAT6T8DOUTECE313Fall2006Lecture20-Memory26/89T1~T4T5T6T7T8A′ADIN位線A位線A′列地址選擇行地址選擇寫放寫放讀放DOUT寫選擇讀選擇靜態(tài)RAM基本電路的寫

操作行選T5、T6開兩個(gè)寫放DIN列選T7、T8開（左）

反相T5A′（右）

T8T6ADINDINT7ECE313Fall2006Lecture20-Memory27/89靜態(tài)RAM芯片舉例-Intel2114存儲容量1K×4位......I/O1I/O2I/O3I/O4A0A8A9WECSCCVGNDIntel2114這些存儲元件應(yīng)該如何排列？才能給出一個(gè)存儲單元的地址而一次讀出4位信息。1、立體；2、平面ECE313Fall2006Lecture20-Memory28/89Intel2114RAM矩陣(64×64)讀A3A4A5A6A7A8A0A1A2A915…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS第一組第二組第三組第四組ECE313Fall2006Lecture20-Memory29/8915…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS第一組第二組第三組第四組0000000000Intel2114RAM矩陣(64×64)讀ECE313Fall2006Lecture20-Memory30/89第一組第二組第三組第四組15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000Intel2114RAM矩陣(64×64)讀150311647326348…………ECE313Fall2006Lecture20-Memory31/89第一組第二組第三組第四組Intel2114RAM矩陣(64×64)讀15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000150311647326348…………ECE313Fall2006Lecture20-Memory32/8915…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000150311647326348…………第一組第二組第三組第四組Intel2114RAM矩陣(64×64)讀0163248CSWEECE313Fall2006Lecture20-Memory33/89第一組第二組第三組第四組Intel2114RAM矩陣(64×64)讀15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECSCSWE150311647326348…………01632480000000000…………ECE313Fall2006Lecture20-Memory34/89第一組第二組第三組第四組Intel2114RAM矩陣(64×64)讀15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000…………CSWE150311647326348…………0163248ECE313Fall2006Lecture20-Memory35/89第一組第二組第三組第四組Intel2114RAM矩陣(64×64)讀15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000…………CSWE150311647326348…………0163248讀寫電路讀寫電路讀寫電路讀寫電路ECE313Fall2006Lecture20-Memory36/89第一組第二組第三組第四組Intel2114RAM矩陣(64×64)讀15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000…………CSWE讀寫電路讀寫電路讀寫電路讀寫電路150311647326348…………0163248I/O1I/O2I/O3I/O4ECE313Fall2006Lecture20-Memory37/89A3A4A5A6A7A8A0A1A2A915…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫ECE313Fall2006Lecture20-Memory38/8915…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS第一組第二組第三組第四組0000000000Intel2114

RAM矩陣(64×64)寫ECE313Fall2006Lecture20-Memory39/89第一組第二組第三組第四組15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000Intel2114

RAM矩陣(64×64)寫150311647326348…………ECE313Fall2006Lecture20-Memory40/89第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼I/O1I/O2I/O3I/O4WECS0000000000150311647326348…………WECSECE313Fall2006Lecture20-Memory41/89第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫I/O1I/O2I/O3I/O4WECS15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼WECS0000000000150311647326348…………WECSI/O1I/O2I/O3I/O4ECE313Fall2006Lecture20-Memory42/89第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫I/O1I/O2I/O3I/O4WECS15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼WECS0000000000150311647326348…………WECSI/O1I/O2I/O3I/O4讀寫電路讀寫電路讀寫電路讀寫電路ECE313Fall2006Lecture20-Memory43/89第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫I/O1I/O2I/O3I/O4WECS15…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼WECS0000000000150311647326348…………WECSI/O1I/O2I/O3I/O4讀寫電路讀寫電路讀寫電路讀寫電路ECE313Fall2006Lecture20-Memory44/89第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫I/O1I/O2I/O3I/O415…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼WECS0000000000150311647326348…………讀寫電路讀寫電路讀寫電路讀寫電路I/O1I/O2I/O3I/O4WECSECE313Fall2006Lecture20-Memory45/89第一組第二組第三組第四組Intel2114

RAM矩陣(64×64)寫I/O1I/O2I/O3I/O415…031…1647…3263…48150311647326348讀寫電路讀寫電路讀寫電路讀寫電路……………………0163015……行地址譯碼列地址譯碼WECS0000000000150311647326348…………I/O1I/O2I/O3I/O4讀寫電路讀寫電路讀寫電路讀寫電路WECS0163248ECE313Fall2006Lecture20-Memory46/89DD預(yù)充電信號讀選擇線寫數(shù)據(jù)線寫選擇線讀數(shù)據(jù)線VCgT4T3T2T11動(dòng)態(tài)RAM(DRAM)-基本單元電路讀出與原存信息相反讀出時(shí)數(shù)據(jù)線有電流為“1”數(shù)據(jù)線CsT字線DDV010110寫入與輸入信息相同寫入時(shí)CS充電為“1”放電為“0”T3T2T1T無電流有電流ECE313Fall2006Lecture20-Memory47/89單元電路讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D行地址譯碼器001131311A9A8A7A6A531A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0…動(dòng)態(tài)RAM芯片舉例-三管動(dòng)態(tài)RAM芯片(Intel1103)讀00000000000D…00單元電路讀寫控制電路ECE313Fall2006Lecture20-Memory48/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0…三管動(dòng)態(tài)RAM芯片(Intel1103)寫ECE313Fall2006Lecture20-Memory49/8911111三管動(dòng)態(tài)RAM芯片(Intel1103)寫A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0…ECE313Fall2006Lecture20-Memory50/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0…11111…三管動(dòng)態(tài)RAM芯片(Intel1103)寫ECE313Fall2006Lecture20-Memory51/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0……0100011111三管動(dòng)態(tài)RAM芯片(Intel1103)寫ECE313Fall2006Lecture20-Memory52/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0……1111110100011三管動(dòng)態(tài)RAM芯片(Intel1103)寫ECE313Fall2006Lecture20-Memory53/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0……D11111010001三管動(dòng)態(tài)RAM芯片(Intel1103)寫ECE313Fall2006Lecture20-Memory54/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0……D11111010001三管動(dòng)態(tài)RAM芯片(Intel1103)寫讀寫控制電路ECE313Fall2006Lecture20-Memory55/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0……D11111010001三管動(dòng)態(tài)RAM芯片(Intel1103)寫讀寫控制電路ECE313Fall2006Lecture20-Memory56/89A9A8A7A6A5讀寫控制電路列地址譯碼器………讀選擇線寫選擇線D單元電路行地址譯碼器00113131131A4A3A2A1A0刷新放大器寫數(shù)據(jù)線讀數(shù)據(jù)線……………0……D11111010001三管動(dòng)態(tài)RAM芯片(Intel1103)寫讀寫控制電路ECE313Fall2006Lecture20-Memory57/89存儲器與CPU的連接-存儲器容量的擴(kuò)展(1)位擴(kuò)展（增加存儲字長）用2片1K

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4位存儲芯片組成1K

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8位的存儲器10根地址線8根數(shù)據(jù)線DD????D0479AA0???21142114CSWEECE313Fall2006Lecture20-Memory58/89(2)字?jǐn)U展（增加存儲字的數(shù)量）用2片1K

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8位存儲芯片組成2K

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8位的存儲器11根地址線8根數(shù)據(jù)線1K

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8位1K

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8位D7D0?????????????????WEA1A0???A9CS0A10

1CS1ECE313Fall2006Lecture20-Memory59/89(3)字、位擴(kuò)展用8片1K

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4位存儲芯片組成4K

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8位的存儲器8根數(shù)據(jù)線12根地址線WEA8A9A0...D7D0……A11A10CS0CS1CS2CS3片選譯碼................1K×41K×41K×41K×41K×41K×41K×41K×4ECE313Fall2006Lecture20-Memory60/89存儲器與CPU的連接的一般步驟

(1)地址線的連接：首選低位地址；(2)數(shù)據(jù)線的連接：位數(shù)要相等；(3)讀/寫線的連接：直接相連；(4)片選線的連接：MREQ和空閑的高地址組合(5)合理選用芯片：RAM/ROM分清(6)其他時(shí)序、負(fù)載Attention:地址線不可懸空，多余的地址線作為控制線，地址線的特定組合決定控制邏輯的設(shè)計(jì)ECE313Fall2006Lecture20-Memory61/89例題：設(shè)CPU有16根地址線，8根數(shù)據(jù)線，用MREQ（低電平有效）作訪存控制信號，用WR作讀/寫控制信號（高電平為讀，低電平為寫）?，F(xiàn)有如下存儲芯片：1Kx4位RAM；4Kx8RAM；8Kx8RAM；2Kx8位ROM；4Kx8ROM；8Kx8ROM，及74L138譯碼器和各種門電路。請畫出CPU與存儲器的連接圖，要求：1、主存地址空間分配6000H~67FFH為系統(tǒng)程序區(qū)6800H~6BFFH為用戶程序區(qū)2、合理選用上述芯片，說明各選幾片？3、畫出存儲芯片的片選邏輯圖ECE313Fall2006Lecture20-Memory62/89(1)寫出對應(yīng)的二進(jìn)制地址碼(2)確定芯片的數(shù)量及類型0110000000000000A15A14A13A11A10…A7…

A4A3…

A0…01100111111111110110100000000000…01101011111111112K×8位1K×8位RAM2片1K×4位ROM1片

2K×8位ECE313Fall2006Lecture20-Memory63/89(3)分配地址線A10~A0接2K

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8位ROM的地址線A9~A0接1K

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4位RAM的地址線(4)確定片選信號CBA0110000000000000A15A13A11A10…A7…

A4A3…

A0…01100111111111110110100000000000…01101011111111112K

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8位1片ROM1K

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4位2片RAMECE313Fall2006Lecture20-Memory64/892K

×8位ROM

1K

×4位

RAM1K

×4位

RAM………&PD/ProgrY5Y4G1CBAG2BG2A……MREQA14A15A13A12A11A10A9A0…D7D4D3D0WR…………CPU與存儲器的連接圖………ECE313Fall2006Lecture20-Memory65/89Outline-MemorySystemsOverview MotivationGeneralStructureandTerminologyMemoryTechnologyStaticRAM DynamicRAMCacheMemory 3VirtualMemoryECE313Fall2006Lecture20-Memory66/89CPUHit:DatainCache(nopenalty)Miss:DatanotinCache(misspenalty)CacheMemoryDRAMMemoryProcessoraddrdataaddrdataCacheOperationInsertbetweenCPU,MainMem.ImplementwithfastStaticRAMHoldssomeofaprogram’sdatainstructionsOperation:ECE313Fall2006Lecture20-Memory67/89FourKeyCacheQuestions:1. Wherecanblockbeplacedincache?

(blockplacement)2. Howcanblockbefoundincache?

(blockidentification)3. Whichblockshouldbereplacedonamiss?

(blockreplacement)4. Whathappensonawrite?

(writestrategy)ECE313Fall2006Lecture20-Memory68/89BasicCacheDesign以塊的方式組織塊的內(nèi)容標(biāo)記tag-extrabitstoidentifyblock(partofblockaddress)數(shù)據(jù)data-dataorinstructionwords -contiguousmemorylocations右邊的例子:每塊一個(gè)字(4byte)Tag為30位Cache中有2個(gè)塊CPUCPUCPUtag0data0CPUCPUtag1data10x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemoryECE313Fall2006Lecture20-Memory69/89CacheExample(2)Assume:r1==0,r2==1,r4==21cycleforcacheaccess5cyclesformain.mem.access1cycleforinstr.executionAtcycle1-PC=0x00FetchinstructionfrommemorylookincacheMISS-fetchfrommainmem

(5cyclepenalty)CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLMISSECE313Fall2006Lecture20-Memory70/89CacheExample(3)Atcycle6Executeinstr.addr1,r1,r2CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…000

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…0ECE313Fall2006Lecture20-Memory71/89CacheExample(4)Atcycle6-PC=0x04FetchinstructionfrommemorylookincacheMISS-fetchfrommainmem

(5cyclepenalty)CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…0MISS6-10 FETCH

0x…4

ECE313Fall2006Lecture20-Memory72/89CacheExample(5)Atcycle11Executeinstr.bner4,r1,LCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…000

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…004

bner4,r1,L0x…111 0x…4 bner4,r1,L

1ECE313Fall2006Lecture20-Memory73/89CacheExample(6)Atcycle11-PC=0x00FetchinstructionfrommemoryHIT-instructionincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…1HIT11 0x…4 bner4,r1,L

111 FETCH0x…0 1ECE313Fall2006Lecture20-Memory74/89CacheExample(7)Atcycle12Executeaddr1,r1,2CPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner1,r2,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 2ECE313Fall2006Lecture20-Memory75/89CacheExample(8)Atcycle12-PC=0x04FetchinstructionfrommemoryHIT-instructionincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x04HITECE313Fall2006Lecture20-Memory76/89CacheExample(9)Atcycle13Executeinstr.bner4,r1,LBranchnottakenCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x0413 bner4,r1,LECE313Fall2006Lecture20-Memory77/89CacheExample(10)Atcycle13-PC=0x08FetchInstructionfromMemoryMISS-notincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x0413 bner4,r1,L13 FETCH0x08MISSECE313Fall2006Lecture20-Memory78/89CacheExample(11)Atcycle17-PC=0x08PutinstructionintocacheReplaceexistinginstructionCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0 112 addr1,r1,2 212 FETCH0x0413 bner4,r1,L13-17 FETCH0x08

subr1,r1,r10x…2ECE313Fall2006Lecture20-Memory79/89CacheExample(12)Atcycle18Executesubr1,r1,r1CPUCPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

16-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0112 addr1,r1,2212 FETCH0x04213 bner4,r1,L213-17 FETCH0x08218 subr1,r1,r10

subr1,r1,r10x…2ECE313Fall2006Lecture20-Memory80/89CacheExample(13)Atcycle18FetchinstructionfrommemoryMISS-notincacheCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCycle Address Op/Instr. r11-5 FETCH

0x…0

6 0x…0 addr1,r1,r2

1L:addr1,r1,r20x…06-10 FETCH

0x…4

bner4,r1,L0x…111 0x…4 bner4,r1,L

112 FETCH0x…0112 addr1,r1,2212 FETCH0x04213 bner4,r1,L213-17 FETCH0x082

subr1,r1,r118 subr1,r1,r1018 FETCH0x0CMISSECE313Fall2006Lecture20-Memory81/89CacheExample(14)Atcycle22PutinstructionintocacheReplaceexistinginstructionCPUCPUCPU(empty)(empty)CPUCPU(empty)(empty)L:addr1,r1,r20x000000000x000000040x000000080x0000000C0x00000000b0b1CacheMainMemory

bner4,r1,L

subr1,r1,r1L:jLCy