Lattice ECP3 FPGA系列AMC評估開發(fā)方案

LatticeECP3FPGA系列AMC評估開發(fā)方案關(guān)鍵詞：AMC,ECP3,FPGA,LatticeLattice公司的LatticeECP3FPGA系列可提供高性能特性如增強(qiáng)的DSP架構(gòu),高速SERDES和高速源同步接口.LatticeECP3采用65nm技術(shù),查找表(LUT)高達(dá)149K邏輯單元,支持高達(dá)486個(gè)用戶I/O,提供高達(dá)320個(gè)18x18乘法器和各種并行I/O標(biāo)準(zhǔn),主要用于對成本和功耗敏感的無線基礎(chǔ)設(shè)備和有線通信.本文介紹了LatticeECP3FPGA主要特性和方框圖,以及LatticeECP3AMC評估板和接口板的主要特性,電路圖以及材料清單(BOM).

TheLatticeECP3?(EConomyPlusThirdgeneration)familyofFPGAdevicesisoptimizedtodeliverhighperformancefeaturessuchasanenhancedDSParchitecture,highspeedSERDESandhighspeedsourcesynchronousinterfacesinaneconomicalFPGAfabric.Thiscombinationisachievedthroughadvancesindevicearchitectureandtheuseof65nmtechnologymakingthedevicessuitableforhigh-volume,high-speed,low-costapplications.TheLatticeECP3devicefamilyexpandslook-up-table(LUT)capacityto149Klogicelementsandsupportsupto486userI/Os.TheLatticeECP3devicefamilyalsooffersupto32018x18multipliersandawiderangeofparallelI/Ostandards.TheLatticeECP3FPGAfabricisoptimizedwithhighperformanceandlowcostinmind.TheLatticeECP3devicesutilizereconfigurableSRAMlogictechnologyandprovidepopularbuildingblockssuchasLUT-basedlogic,distrib-utedandembeddedmemory,PhaseLockedLoops(PLLs),DelayLockedLoops(DLLs),pre-engineeredsourcesynchronousI/Osupport,enhancedsysDSPslicesandadvancedconfigurationsupport,includingencryptionanddual-bootcapabilities.Thepre-engineeredsourcesynchronouslogicimplementedintheLatticeECP3devicefamilysupportsabroadrangeofinterfacestandards,includingDDR3,XGMIIand7:1LVDS.TheLatticeECP3devicefamilyalsofeatureshighspeedSERDESwithdedicatedPCSfunctions.Highjittertoler-anceandlowtransmitjitterallowtheSERDESplusPCSblockstobeconfiguredtosupportanarrayofpopulardataprotocolsincludingPCIExpress,SMPTE,Ethernet(XAUI,GbE,andSGMII)andCPRI.TransmitPre-empha-sisandReceiveEqualizationsettingsmaketheSERDESsuitablefortransmissionandreceptionovervariousformsofmedia.TheLatticeECP3devicesalsoprovideflexible,reliableandsecureconfigurationoptions,suchasdual-bootcapa-bility,bit-streamencryption,andTransFRfieldupgradefeatures.TheispLEVER®designtoolsuitefromLatticeallowslargecomplexdesignstobeefficientlyimplementedusingtheLatticeECP3FPGAfamily.SynthesislibrarysupportforLatticeECP3isavailableforpopularlogicsynthesistools.TheispLEVERtoolusesthesynthesistooloutputalongwiththeconstraintsfromitsfloorplanningtoolstoplaceandroutethedesignintheLatticeECP3device.TheispLEVERtoolextractsthetimingfromtheroutingandback-annotatesitintothedesignfortimingverification.Latticeprovidesmanypre-engineeredIP(IntellectualProperty)ispLeverCORE?modulesfortheLatticeECP3family.ByusingtheseconfigurablesoftcoreIPsasstandardizedblocks,designersarefreetoconcentrateontheuniqueaspectsoftheirdesign,increasingtheirproductivity.

LatticeECP3FPGA主要特性:

HigherLogicDensityforIncreasedSystemIntegration

?17Kto149KLUTs

?133to586I/Os

EmbeddedSERDES

?150Mbpsto3.2GbpsforGeneric8b10b,10-bitSERDES,and8-bitSERDESmodes

?DataRates230Mbpsto3.2Gbpsperchannelforallotherprotocols

?Upto16channelsperdevice:PCIExpress,SONET/SDH,Ethernet(1GbE,SGMII,XAUI),CPRI,SMPTE3GandSerialRapidIO

sysDSP?

?Fullycascadableslicearchitecture

?12to160slicesforhighperformancemultiplyandaccumulate

?Powerful54-bitALUoperations

?TimeDivisionMultiplexingMACSharing

?Roundingandtruncation

?Eachslicesupports

–Half36x36,two18x18orfour9x9multipliers

–Advanced18x36MACand18x18Multiply-Multiply-Accumulate(MMAC)operations

FlexibleMemoryResources

?Upto6.85MbitssysMEM?EmbeddedBlockRAM(EBR)

?36Kto303KbitsdistributedRAM

sysCLOCKAnalogPLLsandDLLs

?TwoDLLsanduptotenPLLsperdevice

Pre-EngineeredSourceSynchronousI/O

?DDRregistersinI/Ocells

?Dedicatedread/writelevellingfunctionality

?Dedicatedgearinglogic

?Sourcesynchronousstandardssupport

–ADC/DAC,7:1LVDS,XGMII

–HighSpeedADC/DACdevices

?DedicatedDDR/DDR2/DDR3memorywithDQSsupport

?OptionalInter-SymbolInterference(ISI)correctiononoutputs

ProgrammablesysI/O?BufferSupportsWideRangeofInterfaces

?On-chiptermination

?Optionalequalizationfilteroninputs

?LVTTLandLVCMOS33/25/18/15/12

?SSTL33/25/18/15I,II

?HSTL15IandHSTL18I,II

?PCIandDifferentialHSTL,SSTL

?LVDS,Bus-LVDS,LVPECL,RSDS,MLVDS

FlexibleDeviceConfiguration

?DedicatedbankforconfigurationI/Os

?SPIbootflashinterface

?Dual-bootimagessupported

?SlaveSPI

?TransFR?I/Oforsimplefieldupdates

?SoftErrorDetectembeddedmacro

SystemLe