VHDL軟件設(shè)計報告

./郵電大學(xué)課程設(shè)計報告設(shè)計類別:EDA-VHDL專業(yè)名稱:電子信息工程班級學(xué)號:B08021717學(xué)生:付祥旭基本題:數(shù)字時鐘設(shè)計綜合題:數(shù)碼管學(xué)號動態(tài)顯示同小組成員：學(xué)號：：曾大千指導(dǎo)教師:王奇、梅中輝、周曉燕、孔凡坤日期：2011年第一章軟件設(shè)計介紹一、 各類設(shè)計環(huán)節(jié)的性質(zhì)、目的與任務(wù)本課程設(shè)計是一門重要的專業(yè)基礎(chǔ)實(shí)踐課,是《現(xiàn)代電子技術(shù)》或《EDA技術(shù)》等課程的后續(xù)實(shí)踐課程,未選前述課程的要求學(xué)生具備數(shù)字電路和C語言的基礎(chǔ)。本課程設(shè)計的目的和任務(wù)：1.使學(xué)生全面了解如何應(yīng)用該硬件描述語言進(jìn)行高速集成電路設(shè)計；2.通過軟件設(shè)計環(huán)節(jié)與仿真環(huán)節(jié)使學(xué)生熟悉QuartusII設(shè)計與仿真環(huán)境；3.通過對基本題、綜合題的設(shè)計實(shí)踐,使學(xué)生掌握硬件系統(tǒng)設(shè)計方法〔自底向上或自頂向下,熟悉VHDL語言三種設(shè)計風(fēng)格,熟悉其芯片硬件實(shí)現(xiàn)的過程。二、實(shí)驗(yàn)容軟件設(shè)計課題共分基本課題、綜合課題兩檔。基本課題2題,12個學(xué)時完成；綜合課題共4題,20個學(xué)時完成。四、考核辦法學(xué)生軟件設(shè)計成績考核來源于以下方面：考勤及工作態(tài)度〔占10％軟件設(shè)計報告〔占40％驗(yàn)收情況〔占50％五、主要設(shè)備微型計算EDA－VHDL開發(fā)軟件〔QUARTUS2ALteraCPLD硬件實(shí)驗(yàn)開發(fā)系統(tǒng)第二章軟件開發(fā)平臺簡介1QuartusII簡介QuartusII提供了完整的多平臺設(shè)計環(huán)境,能滿足各種特定設(shè)計的需要,也是單芯片可編程系統(tǒng)〔SOPC設(shè)計的綜合性環(huán)境和SOPC開發(fā)的基本設(shè)計工具。QuartusII設(shè)計工具完全支持VHDL、Verilog的設(shè)計流程,其部嵌有VHDL、Verilog邏輯綜合器。QuartusII具備仿真功能,同時也支持第三方的仿真工具,如Modelsim。QuartusII包括模塊化的編譯器。編譯器包括的功能模塊有分析/綜合器〔Analysis&Synthesis、適配器<Fitter>、裝配器<Assembler>、時序分析器<TimingAnalyzer>、設(shè)計輔助模塊<DesignAssistant>、EDA網(wǎng)表文件生成器<EDANetlistWriter>、編輯數(shù)據(jù)接口<CompilerDatabaseInterface>等?？梢酝ㄟ^選擇SartCompilation來運(yùn)行所有的編譯器模塊,亦可以通過選擇Start單獨(dú)運(yùn)行各個模塊。還可以通過選擇CompilerTool<Tools菜單>,在CompilerTool窗口中運(yùn)行該模塊來啟動編譯器模塊。在CompilerTool窗口中,可以打開該模塊的設(shè)置文件或報告文件,或打開其他相關(guān)窗口。2QuartusII設(shè)計基本流程=1\*GB3①使用NewProjectWizard〔File菜單建立新工程并指定目標(biāo)器件或器件系列。=2\*GB3②使用TextEditor〔文本編輯器建立VerilogHDL、VHDL或Altera硬件描述語言<AHDL>設(shè)計。也可以使用BlockEditor〔原理圖編輯器建立流程圖或原理圖。流程圖中可以包含代表其它設(shè)計文件的符號。還可以使用MegaWizard?Plug-InManager生成宏功能模塊和IP核的自定義變量,在設(shè)計中將它們實(shí)例化。=3\*GB3③〔可選使用AssignmentEditor、Settings對話框〔Assignments菜單、FloorplanEditor/LogicLock?功能指定初始設(shè)計的約束條件。=4\*GB3④〔可選使用SOPCBuilder或DSPBuilder建立系統(tǒng)級設(shè)計。=5\*GB3⑤〔可選使用SoftwareBuilder為Excalibur?器件處理器或Nios?嵌入式處理器建立軟件和編程文件。=6\*GB3⑥使用Analysis&Synthesis對設(shè)計進(jìn)行綜合。=7\*GB3⑦〔可選使用仿真器對設(shè)計執(zhí)行功能仿真。=8\*GB3⑧使用Fitter對設(shè)計執(zhí)行布局布線。在對源代碼進(jìn)行少量更改之后,還可以使用增量布局布線。=9\*GB3⑨使用TimingAnalyzer對設(shè)計進(jìn)行時序分析。=10\*GB3⑩使用仿真器對設(shè)計進(jìn)行時序仿真。第三章軟件設(shè)計容３.１數(shù)字時鐘設(shè)計１設(shè)計題目及其要求要求學(xué)生設(shè)計一個時鐘,并輸出到數(shù)碼管顯示時,分,秒。2設(shè)計原理注：本實(shí)驗(yàn)設(shè)計采用的是自已購買的開發(fā)板,時鐘為25MHZ,3選8的數(shù)碼管位選,以及共陰型數(shù)碼。電路主要分為分頻電路,選擇電路,計數(shù)電路各譯碼掃描電路。分頻電路:對開板上的晶振產(chǎn)生的25MHZ的調(diào)頻進(jìn)行12.5MHZ的分頻產(chǎn)生1HZ的時鐘信號.選擇電路:對分頻電路產(chǎn)生的1HZ的時鐘信號,和秒計數(shù)器和分計數(shù)產(chǎn)生的進(jìn)位信號進(jìn)行選擇,分別用于校分校時.計數(shù)電路:60計數(shù)器和24的計數(shù)器,分別對秒分和時進(jìn)行計數(shù).60計數(shù)器每計滿60個數(shù)則產(chǎn)生一個進(jìn)位信號,用于作為分鐘計數(shù)器和小時計數(shù)器的時鐘.譯碼掃描電路:對于輸出的秒分時數(shù)據(jù)時行譯,以對應(yīng)8段數(shù)碼管的段選cout1~8,以及位選Key1~3.下面是電路設(shè)計的原理圖：24計數(shù)器24計數(shù)器譯碼與掃描電路ckkS21選擇S11分頻電路選擇60計數(shù)器60計數(shù)器Cout1~8Key1-3圖1：設(shè)計原理圖3、分頻電路因?yàn)榉诸l系數(shù)過大,仿真不具有可操作性,故把先把分頻系數(shù)改小后進(jìn)行仿真。3．1邏輯仿真對輸入CLK1進(jìn)行分頻,得到CLK2。這是把分頻系數(shù)改小后的仿真圖,不代表實(shí)際電路。３．2時序仿真除有一定時間延遲外,與邏輯仿真基本一致。4選擇電路對分頻電路產(chǎn)生的1HZ的時鐘信號,和秒計數(shù)器和分計數(shù)產(chǎn)生的進(jìn)位信號進(jìn)行選擇,分別用于校分校時.4．1邏輯仿真EN1=0CLK=CLK1；EN1=1CLK=CLK2；滿足實(shí)驗(yàn)要求。4．2時序仿真有一定時間延遲外,與邏輯仿真基本一致。5、六十進(jìn)制計數(shù)器5．1邏輯仿真計數(shù)到3B〔16進(jìn)制=60〔10進(jìn)制后產(chǎn)生一個進(jìn)位脈沖,滿足實(shí)驗(yàn)要求。5．2功能仿真有一定時間延遲外,與邏輯仿真基本一致。6、二十四進(jìn)制計數(shù)器6．1邏輯仿真計數(shù)到17〔16進(jìn)制=23〔10進(jìn)制重新從0計數(shù),滿足實(shí)驗(yàn)要求。6．2時序仿真有一定時間延遲外,與邏輯仿真基本一致。7譯碼掃描電路因譯碼掃描電路的正誤碼仿真不具有可觀察性,故不在此仿真。8整體電路仿真8．1邏輯仿真從圖可以看出S1控制校分電路,S2控制校時電路。當(dāng)S1S2=00時,按正常進(jìn)行計時。8．2時序仿真有一定時間延遲外,與邏輯仿真基本一致。9總結(jié)：本題超額完成題目要求,增加了校時校分電路,成為一個真正意義上的時鐘。3．2數(shù)碼管學(xué)號動態(tài)顯示１設(shè)計題目及其要求要求學(xué)生設(shè)計一個時鐘,并輸出到數(shù)碼管顯示時,分,秒。2設(shè)計原理注：本實(shí)驗(yàn)設(shè)計采用的是自已購買的開發(fā)板,時鐘為25MHZ,3選8的數(shù)碼管位選,以及共陰型數(shù)碼。電路主要分為分頻電路,選擇電路,計數(shù)電路各譯碼掃描電路。分頻電路:對開板上的晶振產(chǎn)生的25MHZ時鐘進(jìn)行分頻產(chǎn)生1HZ、2HZ、3HZ、4HZ的時鐘信號.選擇電路:對分頻電路產(chǎn)生的1HZ、2HZ、3HZ、4HZ的時鐘信號,由選擇開關(guān)進(jìn)行選擇電路的時鐘頻率,以控制學(xué)號移動的快慢。循環(huán)電路路：用于控制學(xué)號的循環(huán)左移〔08021717；掃描譯碼電路：譯碼掃描電路:對于輸出的學(xué)號數(shù)據(jù)時行譯,以對應(yīng)8段數(shù)碼管的段選cout1~8,以及位選Key1~3.下面是對設(shè)計原理圖分頻電路選擇電路分頻電路選擇電路循環(huán)電路譯碼掃描電路clkS1,s22Cout1~8Key1~33分頻電路：因?yàn)榉诸l系數(shù)過大,仿真不具有可操作性,故把先把分頻系數(shù)改小后進(jìn)行仿真。3．1邏輯仿真從圖中可以看出輸入一個高頻時鐘信號CLK1,產(chǎn)生四個不同的低頻信號CLK2,CLK3,CLK4,CLK5；滿足實(shí)驗(yàn)要求。３．2時序仿真從圖中可以看出輸入一個高頻時鐘信號CLK1,產(chǎn)生四個不同的低頻信號CLK2,CLK3,CLK4,CLK5；滿足實(shí)驗(yàn)要求。沒有出現(xiàn)毛刺。4選擇電路對分頻電路產(chǎn)生的1HZ、2HZ、3HZ、4HZ的時鐘信號,由選擇開關(guān)進(jìn)行選擇電路的時鐘頻率,以控制學(xué)號移動的快慢。4．1邏輯仿真從圖中可以看出S1S0=‘00’CK=CLK1S1S0=‘01’CK=CLK2S1S0=‘10’CK=CLK3S1S0=‘11’CK=CLK4滿足實(shí)驗(yàn)要求。4．2時序仿真從圖中可以看出S1S0=‘00’CK=CLK1S1S0=‘01’CK=CLK2S1S0=‘10’CK=CLK3S1S0=‘11’CK=CLK4沒出現(xiàn)毛刺,滿足實(shí)驗(yàn)要求。5循環(huán)電路用于控制學(xué)號的循環(huán)左移〔080217175．1邏輯仿真從圖中可以看出每當(dāng)CLK上升沿來臨時,學(xué)號移動一位,并且循環(huán)移動。滿足實(shí)驗(yàn)要求。5．2時序仿真除有一定延時外與邏輯仿真基本一致。6譯碼掃描電路因譯碼掃描電路的正誤碼仿真不具有可觀察性,故不在此仿真。7整體電路仿真7．1邏輯仿真從圖中可以看出學(xué)號循環(huán)移位,并且可以用S11,S10來控制循環(huán)的快慢。邏輯仿真基本一致。7、總結(jié)：完全滿足實(shí)驗(yàn)要求,但在編碼時因做了三個并列較大的分頻,導(dǎo)致資源占用過大。應(yīng)該進(jìn)行多次串聯(lián)分頻,可以大大減少占用資源,代碼有待優(yōu)化。8調(diào)試過程與問題編程和仿真基本上都沒有什么問題,但是在燒錄到芯片時卻出現(xiàn)了一些問題,在些僅舉一個有意義的例子。顯示不穩(wěn)定：是因?yàn)樵趯?shù)碼管加上25MHZ的頻率進(jìn)行數(shù)碼管進(jìn)行掃描時,因?yàn)檫^快,所以導(dǎo)致不穩(wěn)定,一般加在掃描電路上的頻率為幾十到幾百KHZ。9體會與建議體會：本次為期三周的軟件設(shè)計,共完成了一個基本題和一個綜合題。但是因?yàn)槲覍绢}擴(kuò)展了功能〔校時校分,所以比綜合題更顯得復(fù)雜。增強(qiáng)了自己VHDL的編程能力,對VHDL的自頂向下的硬件設(shè)計思想有了更深入的了解。因?yàn)樽约阂郧皩W(xué)過VHDL,對VHDL有一定的了解,并且也做過一個相對比較大的項(xiàng)目,也是采用VHDL編程,所以本次的課題都不大難。在完成課題期間,我認(rèn)為對課題的理解是重中之中,只對對系統(tǒng)的功能有比較深入的了理解,才能保證設(shè)計的合理性和正確性。然后就是自頂向下的思想,如何將一個大型系統(tǒng)分為幾個模塊,然后再把各模塊組合起來,如果能詳細(xì)地分析出各個模塊之間的邏輯關(guān)系,一個復(fù)雜的項(xiàng)目也就顯得很簡單了。各個模塊都是比較基本的,只需要理解VHDL的語言法則,就可以很輕松的完成。我認(rèn)為調(diào)試是系統(tǒng)設(shè)計過程中最難的,也是最痛苦的。這需要設(shè)計者足夠細(xì)心,和有足夠的耐心。因?yàn)椴患?xì)心就會出現(xiàn)很大的錯誤,并且很難找到。查錯能力很重要,這和一個人的編程有經(jīng)驗(yàn)有關(guān),所以要想很快的找出錯誤,減少這個過程的痛苦,只能更多地訓(xùn)練。建議：本次軟件設(shè)計的時間安排比較靈活,均由同學(xué)自已把握,但這樣也使得時間比較零散,很難集中精力。所以我建議應(yīng)該集中安排軟件設(shè)計時間。另外應(yīng)該出一些更有挑戰(zhàn)性的題供選擇。附錄一、數(shù)字時鐘設(shè)計libraryieee;--頂層文件useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityd_clockisport<s1,s2:instd_logic;--校時校分控制開關(guān)ck:instd_logic;--輸入25MHZ的時鐘css:outstd_logic;--數(shù)碼管和點(diǎn)陣現(xiàn)個區(qū)的選擇,CSS=0選擇數(shù)碼管key:outstd_logic_vector<2downto0>;--位選data_out:outstd_logic_vector<7downto0>>;--段選endentityd_clock;architecturebehaveofd_clockiscomponentdf—分頻模塊port<clk1:instd_logic;clk2:bufferstd_logic>;endcomponent;componentc_24--24位計數(shù)器port<clk:instd_logic;cout:outstd_logic_vector<4downto0>>;endcomponentcomponentc_60--60位計數(shù)器port<clk:instd_logic;cc:outstd_logic;cout:outstd_logic_vector<5downto0>>;endcomponent;componentselect2—選擇頻率,即用來校時校分port<clk1,clk2:instd_logic;en1:instd_logic;clk:outstd_logic>;endcomponent;componentshow24—對0~23進(jìn)行譯碼,對應(yīng)數(shù)碼管8段port<tim_data:instd_logic_vector<4downto0>;cout1,cout2:outstd_logic_vector<7downto0>>;endcomponent;componentshow60—對0~59進(jìn)行譯碼,對應(yīng)數(shù)碼管8段port<tim_data:instd_logic_vector<5downto0>;cout1,cout2:outstd_logic_vector<7downto0>>;endcomponent;componentSAOMIAO—動態(tài)掃描電路port<clk:instd_logic;cs:outstd_logic;da1,da2,da3,da4,da5,da6:instd_logic_vector<7downto0>;k:outstd_logic_vector<2downto0>;da:outstd_logic_vector<7downto0>>;endcomponent;signalcp,cp1,cp2,ck1,ck2:std_logic;signalc1,c2:std_logic_vector<5downto0>;signalc3:std_logic_vector<4downto0>;signalten_h,d_h,ten_m,d_m,ten_s,d_s:std_logic_vector<7downto0>;beginu1:dfportmap<clk1=>ck,clk2=>cp>;u2:c_60portmap<clk=>cp,cc=>ck1,cout=>c1>;u3:select2portmap<clk1=>ck1,clk2=>cp,en1=>s1,clk=>cp1>;u4:c_60portmap<clk=>cp1,cc=>ck2,cout=>c2>;u5:select2portmap<clk1=>ck2,clk2=>cp,en1=>s2,clk=>cp2>;u6:c_24portmap<clk=>cp2,cout=>c3>;u7:show60portmap<tim_data=>c1,cout1=>ten_s,cout2=>d_s>;u8:show60portmap<tim_data=>c2,cout1=>ten_m,cout2=>d_m>;u9:show24portmap<tim_data=>c3,cout1=>ten_h,cout2=>d_h>;u10:SAOMIAOportmap<cs=>css,clk=>ck,da1=>ten_h,da2=>d_h,da3=>ten_m,da4=>d_m,da5=>ten_s,da6=>d_s,k=>key,da=>data_out>;endarchitecturebehave;libraryieee;--分頻電路useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitydfisport<clk1:instd_logic;--輸入25MHZclk2:bufferstd_logic>;--輸出1HZendentitydf;architecturebehaveofdfissignalg:std_logic_vector<4downto0>;beginprocess<clk1>beginifclk1'eventandclk1='1'thenif<g="00000000">theng<="00000000";clk2<=notclk2;elseg<=g+"00000001";endif;endif;endprocess;endarchitecturebehave;libraryieee;--24位計數(shù)器useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityc_24isport<clk:instd_logic;--輸入時鐘,來1HZ校時,或者來自分鐘的進(jìn)位cout:outstd_logic_vector<4downto0>—輸出小時的數(shù)據(jù)>;endentityc_24;architecturebehaveofc_24issignalg:std_logic_vector<4downto0>;beginprocess<clk>beginif<clk'eventandclk='1'>thenifg="10111"theng<="00000";elseg<="00001"+g;endif;endif;cout<=g;endprocess;endarchitecturebehave;libraryieee;--60計數(shù)器useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityc_60isport<clk:instd_logic;--輸入時鐘,來自1HZ校分或者是秒計數(shù)時鐘,或者來自秋的進(jìn)位cc:outstd_logic;--秒和分計數(shù)到60產(chǎn)生一個進(jìn)位cout:outstd_logic_vector<5downto0>>;--輸出秒或分鐘的數(shù)據(jù)endentityc_60;architecturebehaveofc_60issignalg:std_logic_vector<5downto0>;beginprocess<clk,g>beginifclk'eventandclk='1'thenifg="111011"theng<="000000";cc<='1';elseg<=g+"000001";cc<='0';endif;endif;cout<=g;endprocess;endarchitecturebehave;libraryieee;--選擇是頻率,即選擇是否校時校分useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityselect2isport<clk1,clk2:instd_logic;--兩個供選擇的頻率en1:instd_logic;--控制開關(guān)clk:outstd_logic>;--輸出被選中的頻率endentityselect2;architecturebehaveofselect2isbeginprocess<clk1,clk2,en1>beginifen1='0'thenclk<=clk1;elseclk<=clk2;endif;endprocess;endarchitecturebehave;libraryieee;--對0~23進(jìn)行譯碼,對應(yīng)數(shù)碼管8段useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityshow24isport<tim_data:instd_logic_vector<4downto0>;--輸入小時數(shù)據(jù)cout1,cout2:outstd_logic_vector<7downto0>>;--輸出十位和個位對應(yīng)的8段數(shù)碼管對應(yīng)的數(shù)據(jù)。endentityshow24;architecturebehaveofshow24issignaltcout1,tcout2:std_logic_vector<7downto0>;beginprocess<tim_data>begincasetim_dataiswhen"00000"=>tcout1<="00000011";tcout2<="00000011";when"00001"=>tcout1<="00000011";tcout2<="10011111";when"00010"=>tcout1<="00000011";tcout2<="00100101";when"00011"=>tcout1<="00000011";tcout2<="00001101";when"00100"=>tcout1<="00000011";tcout2<="10011001";when"00101"=>tcout1<="00000011";tcout2<="01001001";when"00110"=>tcout1<="00000011";tcout2<="01000001";when"00111"=>tcout1<="00000011";tcout2<="00011111";when"01000"=>tcout1<="00000011";tcout2<="00000001";when"01001"=>tcout1<="00000011";tcout2<="00011001";when"01010"=>tcout1<="10011111";tcout2<="00000011";when"01011"=>tcout1<="10011111";tcout2<="10011111";when"01100"=>tcout1<="10011111";tcout2<="00100101";when"01101"=>tcout1<="10011111";tcout2<="00001101";when"01110"=>tcout1<="10011111";tcout2<="10011001";when"01111"=>tcout1<="10011111";tcout2<="01001001";when"10000"=>tcout1<="10011111";tcout2<="01000001";when"10001"=>tcout1<="10011111";tcout2<="00011111";when"10010"=>tcout1<="10011111";tcout2<="00000001";when"10011"=>tcout1<="10011111";tcout2<="00011001";when"10100"=>tcout1<="00100101";tcout2<="00000011";when"10101"=>tcout1<="00100101";tcout2<="10011111";when"10110"=>tcout1<="00100101";tcout2<="00100101";when"10111"=>tcout1<="00100101";tcout2<="00001101";whenothers=>tcout1<="11111111";tcout2<="11111111";endcase;endprocess;cout1<=nottcout1;cout2<=nottcout2;endarchitecturebehave;libraryieee;對0~59進(jìn)行譯碼,對應(yīng)數(shù)碼管8段useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityshow60isport<tim_data:instd_logic_vector<5downto0>;--輸入秒或分鐘的數(shù)據(jù)cout1,cout2:outstd_logic_vector<7downto0>>;--輸出十位和個位對應(yīng)的8段數(shù)碼管endentityshow60;architecturebehaveofshow60issignaltcout1,tcout2:std_logic_vector<7downto0>;beginprocess<tim_data>begincasetim_dataiswhen"000000"=>tcout1<="00000011";tcout2<="00000011";when"000001"=>tcout1<="00000011";tcout2<="10011111";when"000010"=>tcout1<="00000011";tcout2<="00100101";when"000011"=>tcout1<="00000011";tcout2<="00001101";when"000100"=>tcout1<="00000011";tcout2<="10011001";when"000101"=>tcout1<="00000011";tcout2<="01001001";when"000110"=>tcout1<="00000011";tcout2<="01000001";when"000111"=>tcout1<="00000011";tcout2<="00011111";when"001000"=>tcout1<="00000011";tcout2<="00000001";when"001001"=>tcout1<="00000011";tcout2<="00011001";when"001010"=>tcout1<="10011111";tcout2<="00000011";when"001011"=>tcout1<="10011111";tcout2<="10011111";when"001100"=>tcout1<="10011111";tcout2<="00100101";when"001101"=>tcout1<="10011111";tcout2<="00001101";when"001110"=>tcout1<="10011111";tcout2<="10011001";when"001111"=>tcout1<="10011111";tcout2<="01001001";when"010000"=>tcout1<="10011111";tcout2<="01000001";when"010001"=>tcout1<="10011111";tcout2<="00011111";when"010010"=>tcout1<="10011111";tcout2<="00000001";when"010011"=>tcout1<="10011111";tcout2<="00011001";when"010100"=>tcout1<="00100101";tcout2<="00000011";when"010101"=>tcout1<="00100101";tcout2<="10011111";when"010110"=>tcout1<="00100101";tcout2<="00100101";when"010111"=>tcout1<="00100101";tcout2<="00001101";when"011000"=>tcout1<="00100101";tcout2<="10011001";when"011001"=>tcout1<="00100101";tcout2<="01001001";when"011010"=>tcout1<="00100101";tcout2<="01000001";when"011011"=>tcout1<="00100101";tcout2<="00011111";when"011100"=>tcout1<="00100101";tcout2<="00000001";when"011101"=>tcout1<="00100101";tcout2<="00001101";when"011110"=>tcout1<="00001101";tcout2<="00000011";when"011111"=>tcout1<="00001101";tcout2<="10011111";when"100000"=>tcout1<="00001101";tcout2<="00100101";when"100001"=>tcout1<="00001101";tcout2<="00001101";when"100010"=>tcout1<="00001101";tcout2<="10011001";when"100011"=>tcout1<="00001101";tcout2<="01001001";when"100100"=>tcout1<="00001101";tcout2<="01000001";when"100101"=>tcout1<="00001101";tcout2<="00011111";when"100110"=>tcout1<="00001101";tcout2<="00000001";when"100111"=>tcout1<="00001101";tcout2<="00001101";when"101000"=>tcout1<="10011001";tcout2<="00000011";when"101001"=>tcout1<="10011001";tcout2<="10011111";when"101010"=>tcout1<="10011001";tcout2<="00100101";when"101011"=>tcout1<="10011001";tcout2<="00001101";when"101100"=>tcout1<="10011001";tcout2<="10011001";when"101101"=>tcout1<="10011001";tcout2<="01001001";when"101110"=>tcout1<="10011001";tcout2<="01000001";when"101111"=>tcout1<="10011001";tcout2<="00011111";when"110000"=>tcout1<="10011001";tcout2<="00000001";when"110001"=>tcout1<="10011001";tcout2<="00001101";when"110010"=>tcout1<="01001001";tcout2<="00000011";when"110011"=>tcout1<="01001001";tcout2<="10011111";when"110100"=>tcout1<="01001001";tcout2<="00100101";when"110101"=>tcout1<="01001001";tcout2<="00001101";when"110110"=>tcout1<="01001001";tcout2<="10011001";when"110111"=>tcout1<="01001001";tcout2<="01001001";when"111000"=>tcout1<="01001001";tcout2<="01000001";when"111001"=>tcout1<="01001001";tcout2<="00011111";when"111010"=>tcout1<="01001001";tcout2<="00000001";when"111011"=>tcout1<="01001001";tcout2<="00001101";whenothers=>tcout1<="11111111";tcout2<="11111111";endcase;endprocess;cout1<=nottcout1;cout2<=nottcout2;endarchitecturebehave;libraryieee;--掃描電路useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitySAOMIAOisport<clk:instd_logic;--掃描頻率da1,da2,da3,da4,da5,da6:instd_logic_vector<7downto0>;--輸入秒分時的個位十位共六個數(shù)據(jù)k:outstd_logic_vector<2downto0>;--輸出數(shù)碼管的位選cs:outstd_logic;da:outstd_logic_vector<7downto0>>;--輸出段選endentitySAOMIAO;architecturebehaveofSAOMIAOissignalg:std_logic_vector<2downto0>;signaln:integerrange0to25535;signalclk1:std_logic;begincs<='1';process<clk>beginifrising_edge<clk>thenifn=25535thenn<=0;clk1<=notclk1;elsen<=n+1;endif;endif;endprocess;process<clk1>beginifclk1'eventandclk1='1'thenif<g="101">theng<="000";elseg<=g+"001";endif;casegiswhen"000"=>k<="000";da<=da1;when"001"=>k<="001";da<=da2;when"010"=>k<="100";da<=da3;when"011"=>k<="101";da<=da4;when"100"=>k<="010";da<=da5;when"101"=>k<="011";da<=da6;whenothers=>NULL;endcase;endif;endprocess;endarchitecturebehave;附錄二、學(xué)號數(shù)碼管顯示libraryieee;--頂層文件useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitystu_idisport<clk:instd_logic;css:outstd_logic;s1:instd_logic_vector<1downto0>;--控制頻率選擇1、2、3、4HZda_out:outstd_logic_vector<7downto0>;--輸出學(xué)號對應(yīng)的段選k_con:outstd_logic_vector<2downto0>>;--位選endentitystu_id;architecturebehaveofstu_idiscomponentdf—分頻電路port<clk1:instd_logic;clk2,clk3,clk4,clk5:bufferstd_logic>;endcomponent;componentswtch—選擇電路port<s:instd_logic_vector<1downto0>;ck1,ck2,ck3,ck4:instd_logic;ck:outstd_logic>;endcomponent;componentrececle—學(xué)號循環(huán)電路port<clk:instd_logic;c1,c2,c3,c4,c5,c6:bufferstd_logic_vector<3downto0>>;endcomponent;componentym—譯碼電路port<data_in:instd_logic_vector<3downto0>;cout2:outstd_logic_vector<7downto0>>;endcomponent;componentsaomiaois—掃描電路port<clk:instd_logic;cs:outstd_logic;da1,da2,da3,da4,da5,da6:instd_logic_vector<7downto0>;k:outstd_logic_vector<2downto0>;da:outstd_logic_vector<7downto0>>;endcomponent;signalcp,cp1,cp2,cp3,cp4:std_logic;signalid1,id2,id3,id4,id5,id6:std_logic_vector<3downto0>;signalout_d1,out_d2,out_d3,out_d4,out_d5,out_d6:std_logic_vector<7downto0>;beginU1:dfportmap<clk1=>clk,clk2=>cp1,clk3=>cp2,clk4=>cp3,clk5=>cp4>;U0:swtchportmap<s=>s1,ck1=>cp1,ck2=>cp2,ck3=>cp3,ck4=>cp4,ck=>cp>;U2:rececleportmap<clk=>cp,c1=>id1,c2=>id2,c3=>id3,c4=>id4,c5=>id5,c6=>id6>;U4:ymportmap<data_in=>id1,cout2=>out_d1>;U5:ymportmap<data_in=>id2,cout2=>out_d2>;U6:ymportmap<data_in=>id3,cout2=>out_d3>;U7:ymportmap<data_in=>id4,cout2=>out_d4>;U8:ymportmap<data_in=>id5,cout2=>out_d5>;U9:ymportmap<data_in=>id6,cout2=>out_d6>;U10:saomiaoportmap<clk=>clk,cs=>css,da1=>out_d1,da2=>out_d2,da3=>out_d3,da4=>out_d4,da5=>out_d5,da6=>out_d6,k=>k_con,da=>da_out>;endarchitecturebehave;libraryieee;--分頻電路useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entitydfisport<clk1:instd_logic;--輸入25MHZ時鐘clk2,clk3,clk4,clk5:bufferstd_logic>;--輸出1、2、3、4HZ時鐘endentitydf;architecturebehaveofdfissignalg1,g2,g3,g4:std_logic_vector<26downto0>;beginprocess<clk1>beginifclk1'eventandclk1='1'thenif<g1="0000000000">theng1<="0000000000";clk2<=notclk2;elseg1<=g1+"0000000001";endif;ifg2="0000000000"theng2<="0000000000";clk3<=notclk3;elseg2<=g2+"0000000001";endif;ifg3="0000000000"theng3<="0000000000";clk4<=notclk4;elseg3<=g3+"0000000001";endif;if<g4=0000000000">theng4<="0000000000";clk5<=notclk5;elseg4<=g4+"0000000001";endif;endif;endprocess;endarchitecturebehave;libraryieee;--選擇電路useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityswtchisport<s:instd_logic_vector<1downto0>;--選擇開關(guān)ck1,ck2,ck3,ck4:instd_logic;--對應(yīng)1、2、3、4HZ的時鐘ck:outstd_logic>;--輸出被選中的時鐘endentityswtch;architecturebehaveofswtchisbeginprocess<s,ck1,ck2,ck3,ck4>begincasesiswhen"00"=>ck<=ck1;when"01"=>ck<=ck2;when"10"=>ck<=ck3;when"11"=>ck<=ck4;whenothers=>NULL;endcase;endprocess;endarchitecturebehave;libraryieee;--學(xué)號循環(huán)電路useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entityrececleisport<clk:instd_logic;--控制循環(huán)快慢的時鐘c1,c2,c3,c4,c5,c6:bufferstd_logic_vector<3downto0>>;--對應(yīng)學(xué)號的6位endentityrececle;architecturebehaveofrececleissignalg:std_logic_vector<2downto0>;signald1,d2,d3,d4,d5,d6:std_logic_vector<3downto0>;begind1<="0000";d2<="0010";d3<="0001";d4<="0111";d5<="0001";d6<="0111";process<clk>beginif<clk'eventandclk='1'>thenif<g="101">theng<="000";elseg<=g+"001";endif;casegiswhen"000"=>c1<=d1;c2<=d2;c3<=d3;c4<=d4;c5<=d5;c6<=d6;when"001"=>c1<=d2;c2<=