架起電子工業(yè)中芯片封裝和系統(tǒng)仿真之間的橋梁

BridgingamongChip,PackageAndSysteminthe

IndustryElectronicSystemDesign

ChallengesMixed-signalProcessingHigh-FidelityCommunicationCostOptimizedElectronic

SystemsFault-freeEmbedded

CodeLow

PowerCostReductionComplexityManagement2?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017Single-PlatformMultiphysicsandMultiscaleDesignExplorationEncompassingEntireElectronicSystemisNecessaryIndustryReality:SeparatedduetoConventionalEnv.&

SiloEssentialelementscrucialtoperformanceshouldbedecidedby

co-designSeparatedchip,packageandboarddevelopmentownerand

processInsufficientinformation/interestaboutotherpartsdueto

siloNointegratedteamanddesignmethodologyencompassingall

partsDifferentknowledgescope:alientoeach

other#Layers?CoolingDecapReliabilityPerf/Size3?2017ANSYS,

Inc.July31,

2017ANSYSUGM

20174July31,

2017?2017ANSYS,

Inc.ANSYSUGM2017Manual

ConnectionTraditionalPower/Signal/ThermalPerformance

CheckPower

IntegritySignal

IntegrityPackageVSSBumpsVDDBumpsDieStatic&DynamicIRdropw/oPackageManual

ConnectionCanbringinaccurate

resultIBISorXtorThermal

IntegrityPackageor

boardConstantchip

powerChipThermal

ProfileSteady-statewith

onedimensionalBCSystemLevel:Individualpartisdesignedwithitsowntarget

specChipLevel:Chiponlyorlumpedmodel,Manual

ConnectionANSYSChipPackageSystem

ConvergenceThermal

ManagementAntenna

PerformanceTarget

EnvironmentEMI/EMC/ESDChipModelsforsystem

simulationPower,Thermal,Reliability,EMIand

SIPower/SignalIntegrityIC

Power/ReliabilityMechanical

Reliability5?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017Redhawk-CPAPackage/Die

Co-visualizationSystemAwareChipLevelPowerIntegrity

AnalysisInvolvedANSYSproducts:SIwave,

Redhawk/Totem-CPAChip-AwarePackageAC/DChotspot=>

OptimizationBoard&Packageaware

IR/DvDChipdataPkgdataBoardPDN

parasiticExtractionSIwaveRLCGS-parameterIR/AC-HotspotDynamicIRDropat

Cell6?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017ChipAwareSystemLevelPowerIntegrity

AnalysisInvolvedANSYSproductions:SIwave,Redhawk/Totem-CPA,ANSYS

CMAGeneratesfullPDNcoveragecurrent

modelFullPDNperformancecheckthroughAC&transient

simulationANSYS

CMA(ChipModel

Analyzer)FullPDNConnection&

SimulationFullPDNCPM

CreationAC

AnalysisTransient

AnalysisPackage/Boardin

SIwaveRedhawk-CPARLCG/S-parameter7?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017AccurateCurrentModelforFullPDN

Analysis1

MHz10

MHz0

MHz100

MHz1

GHz10

GHz100KHzFullPDNCoverageCurrentModelfromANSYS

CMAMergeTraditionalCPMandmodulated

CurrentCurrentNoisevs.CPM

TypesTimeextensionuptoms8?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017Variousdi/dtforlow/mid.

frequencyTraditional

CPMfrom

RedhwakVoltageDropMitigationbasedonFullPDNCoverage

CPMSystem

Level

PI

Analysis

Case

Study

:

CISCO

&

STVoltagedrop(50mV)withregularCPMbringsveryoptimistic

resultOnlyfullPDNcoverageCPM(=MCPM)detectsseverepower

noisePDNcanbeonlyoptimizedbypowernoiseanalysiswithfullPDN

CPMPowerNoiseDetection&MitigationwithFullPDNCoverage

CPMCorrelationComparisonvs.CPM

types9?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017*SourcedbyDiHu,YongxueYu,AntonioFerrario,OlivierBayet,“SystemPowerNoiseAnalysisUsingModulatedCPM”,IEEE2015ChipAwareSystemLevelSignalIntegrity

AnalysisJEDECTiming

AnalysisPGNoise

AnalysisIBIS/Xtor/CIOMOn-chip

PDNIntrinsicCapof

IOChipModelCreationforSignal

IntegrityChannelConnection&

AnalysisAnsysChipSignal

ModelingJitter

AnalysisRLCG/S-parameterPackage/Boardin

SIwaveForIOCellCharacterizationIOPhysical

Design(GDS/LEF/DEF)IOSpice

Netlist10?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017Accurate&FastChipModelforSignal

IntegrityIBISvs.Xtorvs.

CSM.Spice-levelaccuracywithfullI/Obank

capacity.CapturesimpactofP/Gnoiseon

signal.IBIS/Xtorcanbeavailablein

CSMGlitchFastEasyto

HandleIBISNotAccurateAccurateLackofcapacityLongsimulationHard

togetXtor.Reducedgridcanmodelthousandsof

nodesCSMCIOMreducesruntimefrom64hrs.to24

min.Xtor11?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017CIOMFast&

AccurateSourced

by

“System

Level

PDN

Analysis

EnhancementIncludingI/OSubsystemNoiseModeling”DAC

2013VS.SystemLevelSIAnalysisCaseStudyRootCausingofPLLFailureandGuideRedesignofChip-Package

RoutingNoisefromDDRsignal(B5)activityonPLLPGsupply(VDDAPLL)resultsinPLL

Failure(unlock)Original

PackagePKGredesignA:reducingimpedanceandgroundbouncebymergingPLL_VSSAtochipVSSPKGredesignB:reducingimpedancebyshortingVDDAPLLwithIO

Power(VDDA1.8)Original

PKGPKGredesign

A12?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017PKGredesign

BVoltageDropofVDDAPLLvs.Package

DesignSourcedby“SystemLevelPDNAnalysisEnhancementIncludingI/OSubsystemNoiseModeling”DAC

2013IcePakSystemlevelThermal

simulationSOC PackageChip-Package-SystemThermalAwareReliability

AnalysisChip

ThermalModel(CTM)Boundaryconditions(HTC)PNR

+libraryPkg MCM IPModelIntegratedThermal/selfHeat

AnalysisFullchip

CapacitySeamlessinterfacewith

IcePakAdv.Reliability(post-thermalEM,

FIT)Redhawk-CTA13?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017GenerateThermal

ProfileBack-annotationtochipThermalawareIR/DvD/EM/FIT

AnalysisCaseStudy:Thermal-awareEMforAnalog

IP4.496e-1????????????????=100o

CFIT

Number?????????=41o

CDeviceTemperature

Map4.788e2Δ??=9o

CBEOLDeltaT

Mapw/device

SelfHeat1.283e3ΔT=11o

CBEOLDeltaT

Mapw/deviceandwire2wire

couplingThermalawareEMsign-offisamustforFinFET

designsSource:“AThermal-awareElectromigrationandFailure-in-TimeReliabilityFlow”,XilinxInc.,DAC

201714?2017ANSYS,

Inc.July31,

2017ANSYSUGM

2017CaseStudy:Thermal-awareStatisticalEMfor

SoC????????????@

??????℃2581168%23T=105℃+

???2664197%416No.ofEMviolationsMaxEMviolationTotal

FITSEBidentifycriticalEM

fixesOptimizefor

performanceImprovesproductivityand

TATWireSegmentsviolating

EM“Thermal-awareSEBforAdvancedFinFETEMSign-off”,HisiliconTechnologies,DAC

2017Cumulative

FITCumulativeEMviolationsvs

FITTop200violations

FITof

410So,Fixonly200EM