Jetson Xavier NX Data Sheet 原版完整文件

JETSON|XavierNX|DATASHEET|DA-09366-001|SUBJECTTOCHANGE|COPYRIGHT?2014–2020NVIDIACORPORATION.ALLRIGHTSRESERVED.

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DATASHEET[PRELIMINARY]

NVIDIAJetsonXavierNXSystem-on-Module

VoltaGPU+CarmelARM+8GBLPDDR4x+16GBeMMC5.1

AIPerformance

Upto21TOPS(INT8)

VoltaGPU

384NVIDIA?CUDA?cores|48Tensorcores|End-to-endlosslesscompression|TileCaching|OpenGL?4.6|OpenGLES3.2|Vulkan?1.1?|CUDA10|MaximumOperatingFrequency:1100MHz

CarmelCPU

ARMv8.2(64-bit)heterogeneousmulti-processing(HMP)CPUarchitecture|3xdual-coreCPUclusters(sixNVIDIACarmelprocessorcores)connectedbyahigh-performancesystemcoherencyinterconnectfabric|L3Cache:4MB(sharedacrossallclusters)

NVIDIACarmel(Dual-Core)Processor:L1Cache:128KBL1instructioncache(I-cache)percore;64KBL1datacache(D-cache)percore|L2UnifiedCache:2MBpercluster|MaximumOperatingFrequency:1900MHz

Audio

Dedicatedprogrammableaudioprocessor|ARMCortexA9withNEON|PDMin/out|Industry-standardHighDefinitionAudio(HDA)controllerprovidesamulti-channelaudiopathtotheHDMI?interface

Memory

8GB128-bitLPDDR4xDRAM|SecureExternalMemoryAccessUsingTrustZone?Technology|SystemMMU|MaximumOperatingFrequency:1600MHz

Storage

16GBeMMC5.1FlashStorage|BusWidth:8-bit|MaximumBusFrequency:200MHz(HS400)

Networking

10/100/1000GigabitEthernet|MediaAccessController(MAC)

Imaging

14lanes(3x4or6x2)MIPICSI-2|D-PHY1.2(2.5Gb/sperpair,totalupto30Gbps)

DisplayController

Twomulti-mode(eDP/DP/HDMI)SerialOutputResources(SOR)eDP1.4a|DP1.4|HDMI2.0a/b

MaximumResolution(eDP/DP/HDMI):(upto)3840x2160at60Hz(upto36bpp)

Multi-StreamHDVideoandJPEG

VideoDecode:

Standardssupported:H.265(HEVC),H.264,VP9,

VP8,MPEG-4,MPEG-2,VC-1

2x690MP/sec(HEVC)

2x4K@60(HEVC)

4x4K@30(HEVC)

12x1080p@60(HEVC)

32x1080p@30(HEVC)

16x1080p@30(H.264)

VideoEncode:

Standardssupported:H.265(HEVC),H.264,VP9

2x464MP/sec(HEVC)

2x4K@30(HEVC)

6x1080p@60(HEVC)

14x1080p@30(HEVC)

PeripheralInterfaces

xHCIhostcontrollerwithintegratedPHY(upto)1xUSB3.1,3xUSB2.0|1x1+1x1/2/4PCIe(Gen3)|SD/MMCcontroller(supportingeMMC5.1,SD4.0,SDHOST4.0andSDIO3.0)|3xUART|2xSPI|4xI2C|1xCAN|2xI2S|GPIOs

Mechanical

ModuleSize:69.6mmx45mm|260pinSO-DIMMConnector

OperatingRequirements

TemperatureRange(TJ)*:-25°C–90°C|SupportedPowerModes:10W–15W|PowerInput:5V

Note:RefertotheSoftwareFeaturessectionofthelatestL4TDevelopmentGuideforalistofsupportedfeatures;allfeaturesmaynotbeavailable.

ProductisbasedonapublishedKhronosSpecificationandisexpectedtopasstheKhronosConformanceProcess.Currentconformancestatuscanbefoundat

/conformance.

*SeetheJetsonXavierNXThermalDesignGuidefordetails

JetsonXavierNXSystem-on-ModuleVoltaGPU+CarmelARM+8GBLPDDR4x+16GBeMMC5.1

JETSON|XavierNX|DATASHEET|DA-09366-001|SUBJECTTOCHANGE|COPYRIGHT?2014–2020NVIDIACORPORATION.ALLRIGHTSRESERVED.

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RevisionHistory

Version

Date

Description

V1.1

February1,2020

Updated:

PCIE0_XXXpinsfromCtrl#0toCtrl#5underPCIePindescriptioninTable9:PCIePinDescriptions

PCIE1_XXXpinsfromCtrl#1toCtrl#4underPCIePindescriptioninTable9:PCIePinDescriptions

PulseWidthModulator(PWM)toreflectfouroutputsinsteadofeightoutputs

SHUTDOWN_REQ*andSYS_RESET*pullupinformationinTable21:PowerandSystemControlPins

Table29:AbsoluteMaximumRatingstoincludetheMountingForceparameter.

MechanicalDrawing

V1.0

November6,2019

Initialrelease.

TableofContents

FunctionalOverview 4

VoltaGPU 4

CarmelCPUComplex 5

MemorySubsystem 5

Memory 6

VideoInputInterfaces 6

MIPICameraSerialInterface(CSI) 6

VideoInput(VI) 9

ImageSignalProcessor(ISP) 9

DisplayController 9

HDMIandDisplayPortInterfaces 11

EmbeddedDisplayPort(eDP) 12

High-DefinitionAudio-VideoSubsystem 13

Multi-StandardVideoDecoder 13

Multi-StandardVideoEncoder 14

JPEGProcessingBlock 14

VideoImageCompositor(VIC) 15

AudioProcessingEngine(APE) 15

HighDefinitionAudio(HDA) 16

InterfaceDescriptions 16

SD/eMMC 16

UniversalSerialBus(USB) 17

PCIExpress(PCIe) 18

SerialPeripheralInterface(SPI) 20

UniversalAsynchronousReceiver/Transmitter(UART) 21

ControllerAreaNetwork(CAN) 22

Inter-ChipCommunication(I2C) 23

Inter-ICSound(I2S) 24

GigabitEthernet 25

Fan 26

PulseWidthModulator(PWM) 26

DeepLearningAccelerator(DLA) 26

PowerandSystemManagement 28

PowerRails 28

PowerDomains/Islands 29

PowerManagementController(PMC) 29

Resets 29

PMIC_BBATT 29

PowerSequencing 29

PowerUp 30

PowerDown 30

PowerStates 30

ONState 31

OFFState 31

SLEEPState 31

ThermalandPowerMonitoring 32

PinDefinitions 33

Power-onResetBehavior 33

SleepBehavior 33

GPIO 34

PinList 35

DCCharacteristics 36

OperatingandAbsoluteMaximumRatings 36

DigitalLogic 37

PackageDrawingandDimensions 38

FunctionalOverview

NVIDIA?JetsonXavier?NXbringsAIsupercomputerperformancetotheedgeinacompactsystem-on-module(SOM)that’ssmallerthanacreditcard.JetsonXavierNXisbuiltaroundalow-powerversionoftheNVIDIAXavierSoC,combiningtheNVIDIAVolta?GPUarchitecturewith64-bitoperatingcapability,integratedadvancedmulti-functionvideoandimageprocessing,andNVIDIADeepLearningAccelerators.

Computeperformanceupto14TOPS(at10W)or21TOPS(at15W)enablestheJetsonXavierNXtorunmultipleneuralnetworksinparallelandprocessdatafrommultiplehigh-resolutionsensorssimultaneously.ItalsooffersauniquecombinationofperformanceandpoweradvantageswitharichsetofI/Os,fromhigh-speedCSIandPCIetolow-speedI2CsandGPIOs,allowingembeddedandedgecomputingdevicesthatdemandincreasedperformancebutareconstrainedbysize,weight,andpowerbudgets.

VoltaGPU

TheGraphicsProcessingCluster(GPC)isadedicatedhardwareblockforcomputing,rasterization,shading,andtexturingofmostoftheGPU’scoregraphicsfunctions.TheGPCiscomprisedofTextureProcessingClusters(TPC),witheachTPCcontainingtwoStreamingMultiprocessor(SM)units,andaRasterEngine.TheSMunitcreates,manages,schedules,andexecutesinstructionsfrommanythreadsinparallel.Rasteroperators(ROPs)continuetobealignedwithL2cacheslicesandmemorycontrollers.TheSMgeometryandpixelprocessingperformancemakeithighlysuitableforrenderingadvanceduserinterfaces,whiletheefficiencyoftheVoltaGPUenablesthisperformanceondeviceswithpower-limitedenvironments.

EachSMispartitionedintofourseparateprocessingblocks(referredtoasSMPs),eachSMPcontainsitsowninstructionbuffer,scheduler,CUDAcores,andTensorcores.InsideeachSMP,CUDAcoresperformpixel/vertex/geometryshadingandphysics/computecalculations,andeachTensorcoreprovidesa4x4x4matrixprocessingarraytoperformmixed-precisionfusedmultiply-add(FMA)mathematicaloperations.Textureunitsperformtexturefilteringandload/storeunitsfetchandsavedatatomemory.SpecialFunctionUnits(SFUs)handletranscendentalandgraphicsinterpolationinstructions.Finally,thePolyMorphEnginehandlesvertexfetch,tessellation,viewporttransform,attributesetup,andstreamoutput.

Features:

End-to-endlosslesscompression

TileCaching

SupportforOpenGL4.6,OpenGLES3.2,Vulkan1.1

AdaptiveScalableTextureCompression(ASTC)LDRprofilesupported

CUDAsupport

Iteratedblend,ROPOpenGL-ESblendmodes

2DBLITfrom3Dclassavoidschannelswitch

2Dcolorcompression

ConstantcolorrenderSMbypass

2x,4x,8xMSAAwithcolorandZcompression

Non-powerof2Dand3Dtextures,FP16texturefiltering

FP16shadersupport

GeometryandVertexattributeinstancing

Parallelpixelprocessing

Early-zreject:Fastrejectionofoccludedpixelsactsasmultiplieronpixelshaderandtextureperformancewhilesavingpowerandbandwidth

Videoprotectionregion

Powersaving:Multiplelevelsofclockgatingforlinearscalingofpower

Table1:GPUOperation

Module

CUDACores

TensorCores

PowerMode

OperatingFrequencyperCore(upto)

JetsonXavierNX

384

48

10W

800MHz

15W

1100MHz

CarmelCPUComplex

TheCPUcomplex(CCPLEX)iscomprisedofthreeCarmeldual-coreCPUclustersinacoherentmulti-processorconfiguration.Ahigh-performanceSystemCoherencyFabric(SCF)connectsallCPUclustersenablingsimultaneousoperationofallCPUcores(asneeded)foratrueheterogeneousmulti-processing(HMP)environment.

Featuresinclude:

NVIDIADynamicCodeOptimization

10-wideSuperscalararchitecture

DynamicbranchpredictionwithaBranchTargetBufferandGlobalHistoryBufferRAMs,areturnstackbuffer,andanindirectpredictor

FullimplementationofARMv8.2ISAcompliantarchitectureincluding:

ARMv8TrustZone

ARMv8.0CryptoISA

TrustedMemory

ARMv8.2-FP16support

128KB4-way-associativeparityprotectedL1instructioncachepercore

64KB4-way-associativeparityprotectedL1datacachepercore

2MB16-way-associativeECCprotectedL2cacheperCPUcluster

4MB16-way-associativeECCprotectedL3cache(sharedacrossallclusters)

PerformanceMonitoring

InterfacetoanexternalGenericInterruptController(vGIC-400)

Supportforpowermanagementwithmultiplepowerdomains

Table2:CPUOperation

Module

PowerMode

CPUCores

CPUMaximumFrequency

JetsonXavierNX

10W

2-core

1.5GHz

4-core

1.2GHz

15W

2-core

1.9GHz

4/6-core

1.4GHz

MemorySubsystem

TheMemorySubsystem(MSS)providesaccesstolocalDRAM,SysRAM,andprovidesaSyncPointInterfaceforinter-processorsignaling.TheMSSsupportsfull-speedI/Ocoherencebyroutingrequeststhroughascalablecoherencefabric.Italsosupportsacomprehensivesetofsafetyandsecuritymechanisms.

Structurally,theMSSconsistsof:

MSSDataBackbone-routesrequestsfromclientstotheMSSHubandresponsesfromMSSHubtotheclients

MSSHub-receivesandarbitratesamongclientrequests,performsSMMUtranslation,andsendsrequeststotheMCF

MemoryControllerFabric(MCF)-performssecuritychecks,feedsI/OcoherentrequeststotheScalableCoherenceFabric(SCF),anddirectsrequeststothemultiplememorychannels

MemoryController(MC)Channels-rowsorter/arbiterandDRAMcontrollers

DRAMI/O-channel-to-padfabric,DRAMI/Opads,andPLLs

JetsonXavierNXintegratesa128-bitwideLPDDR4xmemoryinterfaceimplementedasfour32-bitchannelswithx16sub-partitions.Thememorycontrollerprovidesasinglereadorwritecommand,plusarowaddresstobothsub-partitionsinthechanneltotransfer64bytes.Italsoprovidesthreeindependentcolumnaddressbitstoeachsub-partition,allowingitaccessdifferent32-bytesectorsofaGOBbetweenthesub-partitions.Itprovidesconnectionsbetweenawidevarietyofclients,

supportingtheirbandwidth,latency,quality-of-serviceneeds,andanyspecialorderingrequirementsthatareneeded.TheMSSsupportsavarietyofsecurityandsafetyfeaturesandaddresstranslationforclientsthatusevirtualaddresses.

Features:

LPDDR4x:x32DRAMchips

128-bitwidedatabus

Lowlatencypathandfastread/responsepathsupportfortheCPUcomplexcluster

Supportforlow-powermodes:

Softwarecontrollableentry/exitfromself-refresh,powerdown,anddeeppowerdown

Hardwaredynamicentry/exitfrompowerdown,self-refresh

PadsuseDPDmodeduringidleperiods

High-bandwidthinterfacetotheintegratedVoltaGPU

Full-speedI/OcoherencewithbypassforIsochronous(ISO)traffic

SystemMemory-ManagementUnit(SMMU)foraddresstranslationbasedontheARMSMMU-500

High-bandwidthPCIeorderedwrites

AES-XTSencryptionwith128-bitkey

Memory

TheJetsonXavierNXintegrates8GB128-bitLPDDR4xDRAM.Maximumfrequencyof1600MHzhasatheoreticalpeakmemorybandwidthof51.2GB/s.

TheMemoryController(MC)maximizesmemoryutilizationwhileprovidingminimumlatencyaccessforcriticalCPUrequests.Anarbiterisusedtoprioritizerequests,optimizingmemoryaccessefficiencyandutilizationandminimizingsystempowerconsumption.TheMCprovidesaccesstomainmemoryforallinternaldevices.Itprovidesanabstractviewofmemorytoitsclientsviastandardizedinterfaces,allowingtheclientstoignoredetailsofthememoryhierarchy.Itoptimizesaccesstosharedmemoryresources,balancinglatencyandefficiencytoprovidebestsystemperformance,basedonprogrammableparameters.

Features:

TrustZone(TZ)SecureandOS-protectionregions

SystemMemoryManagementUnit

DualCKEsignalsfordynamicpowerdownperdevice

DynamicEntry/ExitfromSelf-RefreshandPowerDownstates

VideoInputInterfaces

MIPICameraSerialInterface(CSI)

Standard

MIPICSI2.0Receiverspecification

MIPID-PHY?v1.2PhysicalLayerspecification

TheNVIDIACameraSerialInterface(NVCSI)workswiththeVideoInput(VI)unittocaptureanimagefromasensor,whereNVCSIisasourceofpixeldatatoVI.NVCSIworksinstreamingmodewhileVIcapturestherequiredframesusingasingle-shotmodeofoperation.AllsyncpointgenerationforsoftwareishandledatVI;thedelaybetweenNVCSIandVIisnegligibleinsoftwareterms.NVCSIdoesnothaveadirectmemoryport,insteaditsendsthepixeldatatomemorythroughtheVI.

Fifth-generationNVIDIAcamerasolution(NVCSI2.0,VI5.0,andISP5.0)providesacombinationhostthatsupportsenhancedMIPID-PHY(withlanedeskewsupport)physicallayeroptionsinthree4-laneorsix2-laneconfigurations;orcombinationsofthese.Eachlanecansupportupto16virtualchannels(VC)andsupportsdatatypeinterleaving.

VirtualChannelInterleaving:VCsaredefinedintheCSI-2specificationandareusefulwhensupportingmultiplecamerasensors.WiththeVCcapability,aone-pixelparser(PP)cande-interleaveupto16imagestreams.

DataTypeInterleaving:InHDRline-by-linemode,thesensorcanoutputlong/shortexposurelinesusingthesameVCandadifferentprogrammabledatatype(DT).

FrequencyTarget:Theparallelpixelprocessingrate,measuredinpixels-per-clock(PPC),isincreasedtoallowhigherthroughputandlowerclockspeeds.Tosupporthigherbandwidthwithoutincreasingtheoperatingfrequency,thehostprocessesmultiplepixelsinoneclock.NVCSIiscapableofprocessingfourPPCswhenbits-per-pixel(BPP)isgreaterthan16,andeightPPCwhenBPPislessthanorequalto16.

WiththenewstreamingmodeinNVCSI,onePPcanhandlealltraffic(embeddeddataandimagedata)fromonecameradevice,including16VCs.

Features:

SupportstheMIPID-PHYv1.2physicallayeroption:

MIPID-PHYsupportsupto2.5Gbits/secperpair,foranaggregatebandwidthof30Gbpsfrom12pairs

BasedonMIPICSI-2v2.0protocolstack

Includessix-pixelparsers(PP)

Supportsupto16virtualchannelsperactivePP

Supportedinputdataformats:

RGB:RGB888,RGB666,RGB565,RGB555,RGB444

YUV:YUV422-8b,YUV420-8b(legacy),YUV420-8b,YUV444-8b

RAW:RAW6,RAW7,RAW8,RAW10,RAW12,RAW14,RAW16,RAW20

DPCM(predictor1):14-10-14,14-8-14,12-8-12,12-7-12,12-6-12,12-10-12,10-8-10,10-7-10,10-6-10

(Predictor2notsupported)

Datatypeinterleavesupport

Table3:CSIPinDescriptions

Pin#

SignalName

Description

Direction

PinType

10

CSI0_CLK_N

Camera,CSI0Clock–

Input

MIPID-PHY

12

CSI0_CLK_P

Camera,CSI0Clock+

Input

MIPID-PHY

4

CSI0_D0_N

Camera,CSI0Data0–

Input

MIPID-PHY

6

CSI0_D0_P

Camera,CSI0Data0+

Input

MIPID-PHY

16

CSI0_D1_N

Camera,CSI0Data1–

Input

MIPID-PHY

18

CSI0_D1_P

Camera,CSI0Data1+

Input

MIPID-PHY

9

CSI1_CLK_N

Camera,CSI1Clock–

Input

MIPID-PHY

11

CSI1_CLK_P

Camera,CSI1Clock+

Input

MIPID-PHY

3

CSI1_D0_N

Camera,CSI1Data0–

Input

MIPID-PHY

5

CSI1_D0_P

Camera,CSI1Data0+

Input

MIPID-PHY

15

CSI1_D1_N

Camera,CSI1Data1–

Input

MIPID-PHY

17

CSI1_D1_P

Camera,CSI1Data1+

Input

MIPID-PHY

28

CSI2_CLK_N

Camera,CSI2Clock–

Input

MIPID-PHY

30

CSI2_CLK_P

Camera,CSI2Clock+

Input

MIPID-PHY

22

CSI2_D0_N

Camera,CSI2Data0–

Input

MIPID-PHY

24

CSI2_D0_P

Camera,CSI2Data0+

Input

MIPID-PHY

34

CSI2_D1_N

Camera,CSI2Data1–

Input

MIPID-PHY

36

CSI2_D1_P

Camera,CSI2Data1+

Input

MIPID-PHY

Pin#

SignalName

Description

Direction

PinType

27

CSI3_CLK_N

Camera,CSI3Clock–

Input

MIPID-PHY

29

CSI3_CLK_P

Camera,CSI3Clock+

Input

MIPID-PHY

21

CSI3_D0_N

Camera,CSI3Data0–

Input

MIPID-PHY

23

CSI3_D0_P

Camera,CSI3Data0+

Input

MIPID-PHY

33

CSI3_D1_N

Camera,CSI3Data1–

Input

MIPID-PHY

35

CSI3_D1_P

Camera,CSI3Data1+

Input

MIPID-PHY

52

CSI4_CLK_N

Camera,CSI4Clock–

Input

MIPID-PHY

54

CSI4_CLK_P

Camera,CSI4Clock+

Input

MIPID-PHY

46

CSI4_D0_N

Camera,CSI4Data0–

Input

MIPID-PHY

48

CSI4_D0_P

Camera,CSI4Data0+

Input

MIPID-PHY

58

CSI4_D1_N

Camera,CSI4Data1–

Input

MIPID-PHY

60

CSI4_D1_P

Camera,CSI4Data1+

Input

MIPID-PHY

40

CSI4_D2_N

Camera,CSI4Data2–

Input

MIPID-PHY

42

CSI4_D2_P

Camera,CSI4Data2+

Input

MIPID-PHY

64

CSI4_D3_N

Camera,CSI4Data3–

Input

MIPID-PHY

66

CSI4_D3_P

Camera,CSI4Data3+

Input

MIPID-PHY

76

DSI_CLK_N

Camera,DSIClock–

Input

MIPID-PHY

78

DSI_CLK_P

Camera,DSIClock+

Input

MIPID-PHY

70

DSI_D0_N

Camera,DSIData0–

Input

MIPID-PHY

72

DSI_D0_P

Camera,DSIData0+

Input

MIPID-PHY

82

DSI_D1_N

Camera,DSIData1–

Input

MIPID-PHY

84

DSI_D1_P

Camera,DSIData1+

Input

MIPID-PHY

Table4:CameraPinDescriptions

Pin#

SignalName

Description

Direction

PinType

213

CAM_I2C_SCL

CameraI2CClock.2.2k?pull-upto3.3Vonthemodule.

Bidir

OpenDrain–3.3V

215

CAM_I2C_SDA

CameraI2CData.2.2k?pull-upto3.3Vonthemodule.

Bidir

OpenDrain–3.3V

116

CAM0_MCLK

Camera0ReferenceClock

Output

CMOS–1.8V

114

CAM0_PWDN

Camera0PowerdownorGPIO

Output

CMOS–1.8V

122

CAM1_MCLK

Camera1ReferenceClock

Output

CMOS–1.8V

120

CAM1_PWDN

Camera1PowerdownorGPIO

Output

CMOS–1.8V

VideoInput(VI)

TheVIblockreceivesdatafromtheCSIreceiverandpreparesitforpresentationtosystemmemoryorthededicatedimagesignalprocessorexecutionresources.TheVIblockprovidesformattingforRGB,YCbCr,andrawBayerdatainsupportofseveralcamerausermodels.Thesemodelsincludesingleandmulti-camerasystems,whichmayhaveuptosixactivestreams.TheinputstreamsareobtainedfromMIPIcompliantCMOSsensorcameramodules.

ImageSignalProcessor(ISP)

TheISPmoduletakesdatafromtheVI/CSImoduleormemoryinrawBayerformatandprocessesittoYUVoutput.Theimagingsubsystemsupportsraw(Bayer)imagesensorsupto24millionpixels.AdvancedimageprocessingisusedtoconvertinputtoYUVdataandremoveartifactsintroducedbyhigh-megapixelCMOSsensorsandopticswithupto30-degreeCRA.

Features:

Flexiblepost-processingarchitectureforsupportingcustomcomputervisionandcomputationalimagingoperations

Bayerdomainhardwarenoisereduction

Per-channelblack-levelcompensation

High-orderlens-shadingcompensation

3x3colortransform

Badpixelcorrection

Programmablecoefficientsforde-mosaicwithcolorartifactreduction

Colorartifactreduction:atwo-level(horizontalandvertical)low-passfilteringschemethatisusedtoreduce/removeanycolorartifactsthatmayresultfromBayersignalprocessingandtheeffectsofsamplinganimage.

Enhanceddownscalingquality

Edgeenhancement

Colorandgammacorrection

Programmabletransferfunctioncurve

Color-spaceconversion(RGBtoYUV)

Imagestatisticsgathering(per-channel)

Two256-binimagehistograms

Upto4,096localregionaverages

ACflickerdetection(50Hzand60Hz)

Focusmetricblock

DisplayController

TheJetsonXavierNXintegratesaUnifiedDisplayController(basedontheNVIDIANVDisplayarchitecture)andtwoindependentdisplayoutputs.TheDisplayControllerincludesaPixelProcessingEnginethatfetchespixeldatatobeprocessedfromDRAMandgeneratesuptosixwindowsofrasterizeddisplay-readypixeldata.Theinstructionsforprocessingthepixeldataarecapturedbythedisplaycontroller'sFrontEnd(FE)logic,whichthengeneratestheindividualcontrolsforthevariousstagesofpixelprocessing.ThepixeldatatobeprocessedarefetchedintheIsochronousMemoryHub(IsoHub)thengothroughthespecifiedpixelprocessing,includingmergingthecursor,infourpipestages:Pre-Composition(Pre-comp);Composition(Comp);Post-Composition(Post-comp);andRasterGeneration(RG).Therasterizeddisplay-readypixeldataareavailablefortheseparatepanels/devices(referredtoasdisplayheads)andarefedthroughamulti-channelcrossbarstructuretotheSerialOutputResources(SOR)intheDisplayInterfaceforthestandarddisplayoutputformat,i.e.,DP(DisplayPort)andHigh-DefinitionMultimediaInterface(HDMI).

Eachofthedisplayheadscanberunatanindependentclockrateandeachcandriveadifferentdisplayresolution.Eachofthesixdisplaywindows(A,B,C,D,E,F)canbearbitrarilyassignedtoanyofthedisplayHeadsasrequired,thenconnectedtoanyoneofthedisplayheadsforthedesiredoutputformat.

Features:

IntegratedHDCPkeystorage,noexternalSecureROMrequired

SixwindowsthatcanbeassignedtoanyHead

Onespecial-purposeTrustZoneprotectedwindowonHead0

Maximumrastersize:32768x32768

Maximumactiveregion:8192x8192

Maximuminputsurfacesize:32768x32768

Maximumfetchedsize:8192x8192

Inputsurfacecolorformats:

16-bitRGB:R4G4B4A4,R5G6B5,A1R5G5B5,andR5G5B5A1

24-bitRGB:A8R8G8B8,X8R8G8B8,A8B8G8R8,andX8B8G8R8

32-bitRGB:A2R10G10B10,A2B10G10R10,X2BL10GL10RL10_XRBIAS,andX2BL10GL10RL10_XVYCC

64-bitRGB:R16_G16_B16_A16_NVBIAS,andR16_G16_B16_A16

PackedYUV422:Y8_U8_Y8_V8_N422,andU8_Y8_V8_Y8_N422

SemiPlanarYUV422(8,10,12bpc):

-Y8_V8U8_N422,Y8_V8U8_N422R

-Y10_V10U10_N422,Y10_V10U10_N422R

-Y12_V12U12_N422,Y12_V12U12_N422R

Semi-planarYUV420(8,10,12bpc):

-Y8_V8U8_N420*

-Y10_V10U10_N420*

-Y12_V12U12_N420*

Semi-planarYUV444(8,10,12bpc):

-Y8_V8U8_N444

-Y10_V10U10_N444

-Y12_V12U12_N444

PlanarYUV420(8,10,12bpc):

-Y8_U8_V8_N420

-Y10_U10_V10_N420

-Y12_U12_V12_N420

PlanarYUV444(8,10,12bpc):

-Y8_U8_V8_N444

-Y10_U10_V10_N444

-Y12_U12_V12_N444

Pipelinedepth

16-bpc,[-1.5,2.5]range(tworangeextensionbits):De-gammawillclipto0,1immediatelyontheinput

Vsync(VCOUNTER)andimmediate(HCOUNTER)flipmodes

ImmediateflipsupportedforRGBonly

Immediateflipsoccuratthesecond8-lineboundaryafterthecurrentline

1.

Notes:

2.

3.

4.

CursorcannotbeenabledonaHeadunlesstheHeadhasatleastonewindowgroupattached.Thewindowgroupdoesnotneedtobeenabled.

TrustZonecannotbeenabledunlessHead0hasatleastonewindowgroupattached.Thisdoesnotneedtobeenabled.

Colorformatsmarkedwithanasterisk(*)areprogrammedasY_UVinthedisplaymanuals,andthenbyte-swappedlatertobeY_VU.

10-bpcand12-bpcYUVcolorformatsarepackedinto16-bpccontainers.Thiseffectivelylimitsimmediateflipstonofasterthanoneevery16lines.

HDMIandDisplayPortInterfaces

Standard

Notes

High-DefinitionMultimediaInterface(HDMI)Specification,

Scramblingsupport

version2.0a/b

Clock/4support(1/40bit-rateclock)

HDMI1.4(upto340MHzpixelclockrate)

HDMI2.0(upto594MHzpixelclockrate)

VESADisplayPortStandardVersion1.4

Note: AsingleCECcontrollerissharedbetweenHDMIandDPinterfacesandcanonlybeappliedforuseononeinterface(i.e.,doesnotsupportmultipleinstancesifbothinterfaceswereusedforHDMI).

AstandardDP1.4orHigh-DefinitionMultimediaInterface(HDMI)2.0a/binterfaceissupported.Thesesharethesamesetofinterfacepins,soeitherDisplayPort(DP)orHDMIcanbesupportednatively.Dual-ModeDisplayPort(DP++)canbesupported,inwhichtheDisplayPortconnectorlogicallyoutputsTMDSsignalingtoaDP-to-HDMIdongle.Eachoutputcollectstheoutputofadisplaypipelinefromthedisplaycontroller,formats/encodesthatoutput(toadesiredformat),andthenstreamsittoanoutputdevice.Eachoutputcanprovideaninterfacetoanexternaldevice;eachoutputcandriveonlyasingleoutputdeviceatanygiventime.HDMIsupportprovidesamethodoftransferringbothaudioandvideodata;theSORreceivesvideofromthedisplaycontrollerandaudiofromaseparatehigh-definitionaudio(HDA)controller,itcombinesandtransmitsthemasappropriate.

Features:

DisplayPort

MultichannelaudiofromHDAcontroller,uptoeightchannels,96kHz,24-bit

DP1.4supportsHBR3at8.1Gbps

(upto)540MHzpixelclockrate(i.e.,1.62GHzforRBR,2.7GHzforHBR,5.4GHzforHBR2,and8.1GbpsforHBR3.

8b/10bencodingsupport

Externaldual-modestandardsupport

Audiostreamingsupport

HDMI

(upto)594MHzpixelclock

8/12bpcRGBandYUV444

-8/10/12bpcYUV422

8bpcYUV420(10/12bpcYUVframebuffersshouldbeoutputasYUV422)

HDMIVendor-SpecificInfoframe(VSI)packettransmission

OnHDMI,multichannelaudiofromHDAcontroller,uptoeightchannels,192kHz,24-bit.

FusecalibrationinformationforHDMIanalogparameter(s)

1080ioutputonHDMI

DPorHDMIconnectorsviaappropriateexternallevelshifting

HDCP2.2and1.4overeitherDPorHDMI

Note:refertoNVIDIAsoftwarereleasenotesfordetailedspecifications.

ExternalDualModestandard(DP2HDMIpassiveoractiveadaptersandadapterdiscovery)

Genericinfoframetransmission

Frame-packed3Dstereomode

Table5:HDMI/DisplayPort/eDPPinDescriptions

Pin#

SignalName

Description

Direction

PinType

39

DP0_TXD0_N

DisplayPort0Lane0orHDMILane2–

Output

AC-Coupledoncarrierboard

41

DP0_TXD0_P

DisplayPort0Lane0orHDMILane2+

Output

AC-Coupledoncarrierboard

45

DP0_TXD1_N

DisplayPort0orHDMILane1–

Output

AC-Coupledoncarrierboard

Pin#

SignalName

Description

Direction

PinType

47

DP0_TXD1_P

DisplayPort0orHDMILane1+

Output

AC-Coupledoncarrierboard

51

DP0_TXD2_N

DisplayPort0Lane2–orHDMILane0–

Output

AC-Coupledoncarrierboard

53

DP0_TXD2_P

DisplayPort0Lane2+orHDMILane0+

Output

AC-Coupledoncarrierboard

57

DP0_TXD3_N

DisplayPort0Lane3–orHDMIClkLane–

Output

AC-Coupledoncarrierboard

59

DP0_TXD3_P

DisplayPort0Lane3+orHDMIClkLane+

Output

AC-Coupledoncarrierboard

90

DP0_AUX_N

DisplayPort0