外文翻譯--AT89S51概述.doc

TheDescriptionofAT89S511GeneralDescriptionTheAT89S51isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmelshigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer.Bycombiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S51providesthefollowingstandardfeatures:4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.2PortsPort0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification.Externalpull-upsarerequiredduringprogramverification.Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseoftheinternalpull-ups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryanddur-ingaccessestoexternaldatamemorythatuse16-bitaddresses(MOVXDPTR).Inthisapplication,Port2usesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVXRI),Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsduringFlashprogram-mingandverification.Port3isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort3outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort3pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL)becauseofthepull-ups.Port3receivessomecontrolsignalsforFlashprogrammingandverification.Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89S51,asshowninthefol-lowingtable.3SpecialFunctionRegistersAmapoftheon-chipmemoryareacalledtheSpecialFunctionRegister(SFR)spaceisshowninTable5-1.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimple-mentedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfea-tures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.InterruptRegisters:TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthefiveinterruptsourcesintheIPregister.DualDataPointerRegisters:Tofacilitateaccessingbothinternalandexternaldatamemory,twobanksof16-bitDataPointerRegistersareprovided:DP0atSFRaddresslocations82H-83HandDP1at84H-85H.BitDPS=0inSFRAUXR1selectsDP0andDPS=1selectsDP1.TheusershouldALWAYSinitializetheDPSbittotheappropriatevaluebeforeaccessingtherespectiveDataPointerRegister.PowerOffFlag:ThePowerOffFlag(POF)islocatedatbit4(PCON.4)inthePCONSFR.POFissetto“1”duringpowerup.Itcanbesetandrestundersoftwarecontrolandisnotaffectedbyreset.4MemoryOrganizationMCS-51deviceshaveaseparateaddressspaceforProgramandDataMemory.Upto64KbyteseachofexternalProgramandDataMemorycanbeaddressed.4.1ProgramMemoryIftheEApinisconnectedtoGND,allprogramfetchesaredirectedtoexternalmemory.OntheAT89S51,ifEAisconnectedtoVCC,programfetchestoaddresses0000HthroughFFFHaredirectedtointernalmemoryandfetchestoaddresses1000HthroughFFFFHaredirectedtoexternalmemory.4.2DataMemoryTheAT89S51implements128bytesofon-chipRAM.The128bytesareaccessibleviadirectandindirectaddressingmodes.Stackoperationsareexamplesofindirectaddressing,sothe128bytesofdataRAMareavailableasstackspace.7.WatchdogTimer(One-timeEnabledwithReset-out)TheWDTisintendedasarecoverymethodinsituationswheretheCPUmaybesubjectedtosoftwareupsets.TheWDTconsistsofa14-bitcounterandtheWatchdogTimerReset(WDTRST)SFR.TheWDTisdefaultedtodisablefromexitingreset.ToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.TheWDTtimeoutperiodisdependentontheexternalclockfrequency.ThereisnowaytodisabletheWDTexceptthroughreset(eitherhardwareresetorWDToverflowreset).WhenWDTover-flows,itwilldriveanoutputRESETHIGHpulseattheRSTpin.5UsingtheWDTToenabletheWDT,ausermustwrite01EHand0E1HinsequencetotheWDTRSTregister(SFRlocation0A6H).WhentheWDTisenabled,theuserneedstoserviceitbywriting01EHand0E1HtoWDTRSTtoavoidaWDToverflow.The14-bitcounteroverflowswhenitreaches16383(3FFFH),andthiswillresetthedevice.WhentheWDTisenabled,itwillincrementeverymachinecyclewhiletheoscillatorisrunning.ThismeanstheusermustresettheWDTatleastevery16383machinecycles.ToresettheWDTtheusermustwrite01EHand0E1HtoWDTRST.WDTRSTisawrite-onlyregister.TheWDTcountercannotbereadorwritten.WhenWDToverflows,itwillgenerateanoutputRESETpulseattheRSTpin.TheRESETpulsedura-tionis98xTOSC,whereTOSC=1/FOSC.TomakethebestuseoftheWDT,itshouldbeservicedinthosesectionsofcodethatwillperiodicallybeexecutedwithinthetimerequiredtopreventaWDTreset.InPower-downmodetheoscillatorstops,whichmeanstheWDTalsostops.WhileinPower-downmode,theuserdoesnotneedtoservicetheWDT.TherearetwomethodsofexitingPower-downmode:byahardwareresetorviaalevel-activatedexternalinterrupt,whichisenabledpriortoenteringPower-downmode.WhenPower-downisexitedwithhardwarereset,servicingtheWDTshouldoccurasitnormallydoeswhenevertheAT89S51isreset.ExitingPower-downwithaninterruptissignificantlydifferent.Theinterruptisheldlowlongenoughfortheoscillatortostabilize.Whentheinterruptisbroughthigh,theinterruptisserviced.TopreventtheWDTfromresettingthedevicewhiletheinterruptpinisheldlow,theWDTisnotstarteduntiltheinterruptispulledhigh.ItissuggestedthattheWDTberesetduringtheinterruptservicefortheinterruptusedtoexitPower-downmode.ToensurethattheWDTdoesnotoverflowwithinafewstatesofexitingPower-down,itisbesttoresettheWDTjustbeforeenteringPower-downmode.BeforegoingintotheIDLEmode,theWDIDLEbitinSFRAUXRisusedtodeterminewhethertheWDTcontinuestocountifenabled.TheWDTkeepscountingduringIDLE(WDIDLEbit=0)asthedefaultstate.TopreventtheWDTfromresettingtheAT89S51whileinIDLEmode,theusershouldalwayssetupatimerthatwillperiodicallyexitIDLE,servicetheWDT,andreenterIDLEmode.WithWDIDLEbitenabled,theWDTwillstoptocountinIDLEmodeandresumesthecountuponexitfromIDLE.Timer0andTimer1intheAT89S51operatethesamewayasTimer0andTimer1intheAT89C51.Forfurtherinformationonthetimersoperation,pleaseclickonthedocumentlinkbelow:/dyn/resources/prod_documents/DOC4316.PDF6InterruptsTheAT89S51hasatotaloffiveinterruptvectors:twoexternalinterrupts(INT0andINT1),twotimerinterrupts(Timers0and1),andtheserialportinterrupt.TheseinterruptsareallshowninFigure10-1.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunct