單片機(jī)溫度控制系統(tǒng)中英文翻譯資料

1、英文原文descriptionthe at89s52 is a low-power, high-performance cmos 8-bit microcomputer with 4k bytes of flash programmable and erasable read only memory (perom) and 128 bytes ram. the device is manufactured using atmels high density nonvolatile memory technology and is compatible with the industry sta

2、ndard mcs-51 instruction set and pinout. the chip combines a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89s52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.features: compatible with mcs-51 products

3、 4k bytes of in-system reprogrammable flash memory endurance: 1,000 write/erase cycles fully static operation: 0 hz to 24 mhz three-level program memory lock 128 x 8-bit internal ram 32 programmable i/o lines two 16-bit timer/counters six interrupt sources programmable serial channel low power idle

4、and power down modesthe at89s52 provides the following standard features: 4k bytes of flash, 128 bytes of ram, 32 i/o lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. in addition, the at89s52 is desig

5、ned with static logic for operation down to zero frequency and supports two software selectable power saving modes. the idle mode stops the cpu while allowing the ram, timer/counters, serial port and interrupt system to continue functioning. the power down mode saves the ram contents but freezes the

6、 oscillator disabling all other chip functions until the next hardware reset.pin description:vcc supply voltage.gnd ground.port 0port 0 is an 8-bit open drain bidirectional i/o port. as an output port each pin can sink eight ttl inputs. when is are written to port 0 pins, the pins can be used as hig

7、h impedance inputs. port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. in this mode p0 has internal pullups. port 0 also receives the code bytes during flash programming, and outputs the code bytes during program verific

8、ation. external pullups are required during program verification.port 1port 1 is an 8-bit bidirectional i/o port with internal pullups. the port 1 output buffers can sink/source four ttl inputs. when 1s are written to port 1 pins they are pulled high by the internal pullups and can be used as inputs

9、. as inputs, port 1 pins that are externally being pulled low will source current (iil) because of the internal pullups. port 1 also receives the low-order address bytes during flash programming and verification.port 2port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output

10、 buffers can sink/source four ttl inputs. when 1s are written to port 2 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current (iil) because of the internal pullups. port 2 emits the high-order addr

11、ess byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx dptr). in this application it uses strong internal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri), port 2 emits the

12、contents of the p2 special function register. port 2 also receives the high-order address bits and some control signals during flash programming and verification.port 3port 3 is an 8-bit bidirectional i/o port with internal pullups. the port 3 output buffers can sink/source four ttl inputs. when 1s

13、are written to port 3 pins they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current (iil) because of the pullups. port 3 also serves the functions of various special features of the at89s52 as listed below

14、:port pinalternate functionsp3.0rxd (serial input port)p3.1txd (serial output port)p3.2int0 (external interrupt0)p3.3int1 (external interrupt1)p3.4t0 (timer0 external input)p3.5t1 (timer1 external input)p3.6 wr (external data memory write strobe)p3.7rd (external data memory read strobe)port 3 also r

15、eceives some control signals for flash programming and verification.rstreset input. a high on this pin for two machine cycles while the oscillator is running resets the device.ale/progaddress latch enable output pulse for latching the low byte of the address during accesses to external memory. this

16、pin is also the program pulse input (prog) during flash programming.in normal operation ale is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. note, however, that one ale pulse is skipped during each access to external data memory

17、. if desired, ale operation can be disabled by setting bit 0 of sfr location 8eh. with the bit set, ale is active only during a movx or movc instruction. otherwise, the pin is weakly pulled high. setting the ale-disable bit has no effect if the microcontroller is in external execution mode.psenprogr

18、am store enable is the read strobe to external program memory. when the at89s52 is executing code from external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory.ea/vppexternal access enable. ea must be

19、 strapped to gnd in order to enable the device to fetch code from external program memory locations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to vcc for internal program executions. this pin also rece

20、ives the 12-volt programming enable voltage(vpp) during flash programming, for parts that require 12-volt vpp.xtal1input to the inverting oscillator amplifier and input to the internal clock operating circuit.xtal2output from the inverting oscillator amplifier.oscillator characteristicsxtal1 and xta

21、l2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 1. either a quartz crystal or ceramic resonator may be used. to drive the device from an external clock source, xtal2 should be left unconnected while xta

22、l1 is driven as shown in figure 2. there are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.idle modein idle mod

23、e, the cpu puts itself to sleep while all the onchip peripherals remain active. the mode is invoked by software. the content of the on-chip ram and all the special functions registers remain unchanged during this mode. the idle mode can be terminated by any enabled interrupt or by a hardware reset.i

24、t should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the po

25、rt pins is not inhibited. to eliminate the possibility of an unexpected write to a port pin when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. status of external pins during idle and power down mode

26、smodeprogram memoryalepsenport0 port1port2port3idleinternal11datadatadatadataidleexternal11floatdatadatadatapower downinternal00datadatadatadatapower downexternal 00floatdatadatadatapower down modein the power down mode the oscillator is stopped, and the instruction that invokes power down is the la

27、st instruction executed. the on-chip ram and special function registers retain their values until the power down mode is terminated. the only exit from power down is a hardware reset. reset redefines the sfrs but does not change the on-chip ram. the reset should not be activated before vcc is restor

28、ed to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.program memory lock bitson the chip are three lock bits which can be left unprogrammed (u) or can be programmed (p) to obtain the additional features listed in the table below: lock

29、bit protection modeswhen lock bit 1 is programmed, the logic level at the ea pin is sampled and latched during reset. if the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. it is necessary that the latched value of ea be i

30、n agreement with the current logic level at that pin in order for the device to function properly.programming the flash：the at89s52 is normally shipped with the on-chip flash memory array in the erased state (that is, contents = ffh) and ready to be programmed. the programming interface accepts eith

31、er a high-voltage (12-volt) or a low-voltage (vcc) program enable signal. the low voltage programming mode provides a convenient way to program the at89s52 inside the users system, while the high-voltage programming mode is compatible with conventional third party flash or eprom programmers. the at8

32、9s52 is shipped with either the high-voltage or low-voltage programming mode enabled. the respective top-side marking and device signature codes are listed in the following table.vpp=12vvpp=5vtop-side markat89s52xxxxyywwat89s52xxxx-5yywwsignature(030h)=1eh(031h)=51h(032h)=ffh(030h)=1eh(031h)=51h(032

33、h)=05hthe at89s52 code memory array is programmed byte-bybyte in either programming mode. to program any nonblank byte in the on-chip flash programmable and erasable read only memory, the entire memory must be erased using the chip erase mode.programming algorithm: before programming the at89s52, th

34、e address, data and control signals should be set up according to the flash programming mode table and figures 3 and 4. to program the at89s52, take the following steps.1. input the desired memory location on the address lines.2. input the appropriate data byte on the data lines.3. activate the corr

35、ect combination of control signals.4. raise ea/vpp to 12v for the high-voltage programming mode.5. pulse ale/prog once to program a byte in the flash array or the lock bits. the byte-write cycle is self-timed and typically takes no more than 1.5 ms. repeat steps 1 through 5, changing the address and

36、 data for the entire array or until the end of the object file is reached.data polling: the at89s52 features data polling to indicate the end of a write cycle. during a write cycle, an attempted read of the last byte written will result in the complement of the written datum on po.7. once the write

37、cycle has been completed, true data are valid on all outputs, and the next cycle may begin. data polling may begin any time after a write cycle has been initiated.ready/busy: the progress of byte programming can also be monitored by the rdy/bsy output signal. p3.4 is pulled low after ale goes high d

38、uring programming to indicate busy. p3.4 is pulled high again when programming is done to indicate ready.program verify: if lock bits lb1 and lb2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. the lock bits cannot be verified dire

39、ctly. verification of the lock bits is achieved by observing that their features are enabled.chip erase: the entire flash programmable and erasable read only memory array is erased electrically by using the proper combination of control signals and by holding ale/prog low for 10 ms. the code array i

40、s written with all “1”s. the chip erase operation must be executed before the code memory can be re-programmed.reading the signature bytes: the signature bytes are read by the same procedure as a normal verification of locations 030h, 031h, and 032h, except that p3.6 and p3.7 must be pulled to a log

41、ic low. the values returned are as follows.(030h) = 1eh indicates manufactured by atmel(031h) = 51h indicates 89c51(032h) = ffh indicates 12v programming(032h) = 05h indicates 5v programmingprogramming interfaceevery code byte in the flash array can be written and the entire array can be erased by u

42、sing the appropriate combination of control signals. the write operation cycle is selftimed and once initiated, will automatically time itself to completion.中文翻譯描述at89s52是美國(guó)atmel公司生產(chǎn)的低電壓，高性能cmos8位單片機(jī)，片內(nèi)含4kbytes的快速可擦寫的只讀程序存儲(chǔ)器（perom）和128 bytes的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（ram），器件采用atmel公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)mcs-51產(chǎn)品指令系統(tǒng)

43、，片內(nèi)置通用8位中央處理器（cpu）和flish存儲(chǔ)單元，功能強(qiáng)大at89s52單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)合，可靈活應(yīng)用于各種控制領(lǐng)域。主要性能參數(shù)：與mcs-51產(chǎn)品指令系統(tǒng)完全兼容4k字節(jié)可重復(fù)寫flash閃速存儲(chǔ)器1000次擦寫周期全靜態(tài)操作：0hz24mhz三級(jí)加密程序存儲(chǔ)器128*8字節(jié)內(nèi)部ram32個(gè)可編程i/o口2個(gè)16位定時(shí)計(jì)數(shù)器6個(gè)中斷源可編程串行uart通道低功耗空閑和掉電模式功能特性概述at89s52提供以下標(biāo)準(zhǔn)功能：4k 字節(jié)flish閃速存儲(chǔ)器，128字節(jié)內(nèi)部ram，32個(gè)i/o口線，兩個(gè)16位定時(shí)計(jì)數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振

44、蕩器及時(shí)鐘電路。同時(shí)，at89s52可降至0hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式。空閑方式停止cpu的工作，但允許ram，定時(shí)計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存ram中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。方框圖引腳功能說明vcc：電源電壓gnd：地p0口：p0口是一組8位漏極開路型雙向i/o口，也即地址/數(shù)據(jù)總線復(fù)位口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)邏輯門電路，對(duì)端口寫“1”可 作為高阻抗輸入端用。 在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。p1口：p

45、1是一個(gè)帶內(nèi)部上拉電阻的8位雙向i/o口，p1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)ttl邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可做熟出口。做輸出口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（iil）.flash編程和程序校驗(yàn)期間，p1接受低8位地址。p2口：p2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向i/o口，p2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)ttl邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部地山拉電阻把端口拉到高電平，此時(shí)可作為輸出口，作輸出口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（iil）。在訪問外部程序存

46、儲(chǔ)器獲16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行 movx dptr指令）時(shí)，p2口送出高8位地址數(shù)據(jù)。在訪問8位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行 movx ri指令）時(shí)，p2口線上的內(nèi)容（也即特殊功能寄存器（sfr）區(qū)中r2寄存器的內(nèi)容），在整個(gè)訪問期間不改變。flash編程或校驗(yàn)時(shí)，p2亦接受高地址和其它控制信號(hào)。p3口：p3口是一組帶有內(nèi)部上拉電阻的8位雙向i/o口。p3口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)ttl邏輯門電路。對(duì)p3口寫入“1”時(shí)，他們被內(nèi)部上拉電阻拉高并可作為輸出口。做輸出端時(shí)，被外部拉低的p3口將用上拉電阻輸出電流（iil）。p3口除了作為一般的i/o口線外，更重要的用途是它

47、的第二功能，如下表所示：端口引腳第二功能p3.0rxd (串行輸入口)p3.1txd (串行輸出口)p3.2int0 (外中斷0)p3.3int1 (外中斷1)p3.4t0 (定時(shí)/計(jì)數(shù)器0)p3.5t1 (定時(shí)/計(jì)數(shù)器1)p3.6 wr (外部數(shù)據(jù)存儲(chǔ)器寫選通)p3.7rd (外部數(shù)據(jù)存儲(chǔ)器讀選通)p3口還接收一些用于flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。rst：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，rst引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。ale/prog：當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ale（地址所存允許）輸出脈沖用于所存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ale仍以時(shí)鐘

48、振蕩頻率的1/6輸出固定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ale脈沖。對(duì)flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（prog）。如有不要，可通過對(duì)特殊功能寄存器（sfr）區(qū)中的8eh單元的d0位置位，可禁止ale操作。該外置位后，只要一條movx和movc指令ale才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ale無(wú)效。psen：程序存儲(chǔ)允許（psen）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)at89s52由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩個(gè)psen有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部

49、數(shù)據(jù)存儲(chǔ)器，這兩次有效的psen信號(hào)不出現(xiàn)。ea/vpp:外部訪問允許。欲使cpu僅訪問外部程序存儲(chǔ)器（地址為0000h-ffffh），ea端必須保持低電平（接地）。需注意的是; 如果加密位lb1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存ea端狀態(tài)。如 ea端為高電平（接vcc端），cpu則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。flash存儲(chǔ)器編程時(shí)，該引腳加上+12v的編程允許電源vpp，當(dāng)然這必須是該器件是使用12v編程電壓vpp.xtal1: 振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸出端。xtal2: 振蕩器反相放大器的輸出端。時(shí)鐘振蕩器：at89s52中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳xtal1和x

50、tal2分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體（或陶瓷諧振器）及電容c1、c2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對(duì)外接電容c1、c2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響振蕩頻率的高低、振蕩器的穩(wěn)定性、起振的難易程度及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30pf+10pf，而如使用陶瓷諧振器建議選擇40pf+10pf。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖5右所示。這種情況下，外部時(shí)鐘脈沖接到xtal1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，xtal2則懸空由于外部時(shí)鐘信號(hào)是通過

51、一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)要求。空閑模式:在空閑工作模式狀態(tài)，cpu保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)ram和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激活，即可終止空閑工作模式。程序會(huì)首先響應(yīng)中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序并僅隨終端返回指令，下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入空閑模式那條指令后面的一條指令。其二是通過硬件復(fù)位也可將空閑工

52、作模式終止，需要注意的是，當(dāng)由硬件復(fù)位來(lái)終止空閑模式時(shí)，cpu通常是從激活空閑模式那條指令的下一條指令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期（24個(gè)時(shí)鐘周期）有效，在這種情況下，內(nèi)部禁止cpu訪問片內(nèi)ram，而允許訪問其它端口。為了避免可能對(duì)端口產(chǎn)生以外寫入，激活空閑模式的那條指令后一條指令不應(yīng)該是一條對(duì)端口或外部存儲(chǔ)器的寫入指令?？臻e和掉電模式外部引腳狀態(tài)模式程序存儲(chǔ)器alepsenport0 port1port2port3空閑模式內(nèi)部11數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)空閑模式外部11浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式內(nèi)部00數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式外部00浮空數(shù)據(jù)數(shù)據(jù)數(shù)據(jù)掉電模式:在掉電模式下，震蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)ram和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變r(jià)am中的內(nèi)容，在vcc恢復(fù)到正常工作電平