簡單的FIFO仿真以及程序

1、fifo的仿真。有圖有真相，拋磚引玉 下面是程序：module fifo(clk,rst,/ fifo_wrdb, /dinfifo_rddb,/doutfifo_full,fifo_empty);in put clk;in put rst;/in put7:0fifo_wrdb;output fifo_full;output fifo_empty;/ reg fifo_rdrdy;/fifo讀數(shù)據(jù)有效信號output 7:0fifo_rddb;/fifo讀數(shù)據(jù)總線/wire 7:0fifo_wrdb_r;/assig n fifo_wrdb_r = fifo_wrdb;/定時產(chǎn)生32個FIF

2、O數(shù)據(jù)寫入和讀出操作reg7:0 fifo_wrdb;/FIFO寫入數(shù)據(jù)reg fifo_wren;/FIFO 寫使能信號reg fifo_rden;/FIFO 讀使能信號reg9:0 cnt;always (posedge elk or n egedge rst)if(!rst) ent <= 10'd0;else cnt <= en t+1'b1;always (posedge elk or n egedge rst )if(!rst) beg infifo_wre n <= 1'bO;fifo_rden <= 1'bO;fifo_w

3、rdb <= 8'dO;end/連續(xù)32個FIFO數(shù)據(jù)寫入else if(c nt > 1O'dO) && (cnt < 1O'd33) beginfifo_wre n <= 1'b1;fifo_rden <= 1'bO;fifo_wrdb <= cn t7:0;end/連續(xù)32個FIFO數(shù)據(jù)讀出else if(c nt > 1O'd1OO) && (cnt < 1O'd133) beginfifo_wre n <= 1'bO;fifo_rden

4、 <= 1'b1;fifo_wrdb <= 8'dO;endelse begi nfifo_wre n <= 1'bO;fifo_rden <= 1'bO;fifo_wrdb <= 8'dO;end/*/FIFO讀數(shù)據(jù)有效標志位/ always (posedge clk or n egedge rst)/ if(rst) fifo_rdrdy <= 1'b0;/ else fifo_rdrdy <= fifo_rde n;/*fifo_co ntrollerfifo_c on troller_ck(.cl

5、k(clk), / i nput clk.rst(rst), /input rst.di n(fifo_wrdb), /in put 7 : 0 din.wr_e n(fifo_wre n), / input wr_en.rd_e n(fifo_rde n), /in put rd_e n.dout(fifo_rddb), / output 7 : 0 dout.full(fifo_full), / output full.empty(fifo_empty) / output empty);en dmodule下面是仿真程序：module fifo_text;/ I nputsreg clk;

6、reg rst;/ Outputswire 7:0 fifo_rddb;wire fifo_full;wire fifo_empty;/I nsta ntiate the Unit Under Test (UUT) fifo uut (.clk(clk),.rst(rst),.fifo_rddb(fifo_rddb),.fifo_full(fifo_full),.fifo_empty(fifo_empty);in itial beg in/ I nitialize In putsclk = 1'bO;rst = 1'b0;/fifo_wrdb = 1;/ Wait 100 ns for global reset to finish#100;rst =