OV7670攝像頭徹底解讀

1、2013221【發(fā)憂由孑叢術(shù)爻rthttp：/ amfpga.taobao.comov7670攝像頭徹底解讀序本文解決ov7670開發(fā)的過稈中的3個(gè)問題：1. ov7670是什么;2. ov7670怎么川：3. ov7670怎么用好。文®適合在fpga i：開發(fā)ov7670應(yīng)用的開發(fā)人員。一、ov7670是什么ov7670扱像尖上®特性困 10v7670 攝橡頭主要特 性(源自 j ov7670 preliminary datasheet version 1.4 page 1) 1-傳感器封裝結(jié)構(gòu)ov7670仏感器釘k列兩種封裝形式*2013 2 21【發(fā)憂電孑並術(shù)爻牦ht

2、tp：/ amfpga.taobao.comov7670/ov7171 pin diagram (top view)®®®®avto«0.0«0.cdim® ® ® ® pvttivrfnagkddo(»做” ov7670/ov7171 (x)w 觀hr&®®®®®kmchwofifxeucwtt®®®®的wu>ksft0onmo«cmhdfi|!w2ov7670攝像頭ji

3、裝形式右圖屮行腳、卜：引腳名稱引腳類型功能定義1ncoutputoutput bit0 lsb for 10"bit rgb only2ncoutputoutput bitl - for 10-bit rgb only3y2outputoutput bit44y1outputoutput bit35y3outputoutput bit56y0outputoutput bit2 - lsb for 8bit yuv7y4outputoutput bit68pclkoutputpixel clock output9y5outputoutput bit710dgndpowerdigital

4、 ground11y6outputoutput bit812xclk1inputcrystal clock input13y7outputoutput bit9 - msb for 10-bi t rgb and s_bit yuv11dovddpowerdigital power supply (vdd_io= 2. 5 to 3. 3 vdc)2013-2-21孑並術(shù)爻牦http：/ amfpga.taobao.com15dvddpowerpower supply (vdd-c= 1. 8 vdc + 10%) for digital output drive16hrefoutputhre

5、f output17pwdnfunction(default = 0)power down mode selection active high, internal pull-down resistor. 0:normal mode 1: power down mode18vsyncoutputvertical sync output19resetfunction(default = 0)clears all registers and resets them to their default values. active high, internal pul卜down resistor.20

6、sio-cinputsccb serial interface clock input21avddpoweranalog power supply (vdda= 2. 45 to 2. 8 vdc)22sioj)i/osccb serial interface data i/o23agndpoweranalog ground24nc1. ov7670功能模塊ftl2013 2 21【發(fā)憂電孑並術(shù)爻牦http：/ amfpga.taobao.com| bumr | i buffw ixclk strobe kref pc ik vsync re&eu pwdh4»0_cw0_0

7、圖 3 ov7670 功能模塊圖(源自 r ov7670 preliminary datasheet version 1.4 page 2) rtlffl3可知，校塊由5人部分構(gòu)成.分別2, 1： i?像投數(shù)轉(zhuǎn)換(analog processing)： 2： 測試閣案發(fā)生器(test pattern generator) 3:數(shù)裾輸出:4： 656x488 w像傳感器整列;5:sccb通信接ii 3.1 image sensor arrayov7670仏感脒pl列力656x488.總共介320,128像教點(diǎn).it屮燈效的為640x480. 總k足307,20像累。2.2 timing gene

8、rator旮以k功能：1) 閣像w列控制和陽像幀產(chǎn)生：2) 內(nèi)部時(shí)序信u產(chǎn)生和分發(fā)：3) m率時(shí)序4) 動(dòng)曝)t檸制(aec)相叉布介器« coml=0x04;aechh=0x07;aech=0xl0,com8=0xl3)5)外部吋序輸出(vsynghref/hsync.fil pclk)孑並術(shù)爻牦2o1s-2-21http:/ amfpga.丁aobao.comv7670攝像尖怎么用1. 極像尖迚件屯路所使用攝像尖的電路原理圖如圖4所示。u1為ov7670攝像頭傳感器，采用bga 対裝 p1為外部技11.信巧電甲為3.3vttl,珂以跟3.3v電甲的外沒餼接迮接. vcc為3.3v

9、電壓.在電路上特別要注意的是.sccb的兩根信號線si0_d. si0_c需 賢上拉4.7k電阻。w 5為扱像失稅塊實(shí)物ffl:- 甲0kdam>dal0 da：30 ca3dia4asvcconddob4dovdd fjam®30 d oc did3 ptvdx vrct2 aond dod: dm® mirri vsync hrefpojc stkobe xclkd7 d5 dcato re2t- docra) d604vcc息1ondo bj<瀘jfretpcul7oexclkw10d6kd4d5* im暴參14d21115ixdoipmeader sx2

10、悶4ov7670扱像火投塊電路ku'i'm20132-21孑放術(shù)爻http：/ amfpga.taobao.comm 5 ov7670擬像火投塊實(shí)物ffl2. ov7670 i i 時(shí)汴ov7670接n時(shí)序氈括兩部分:1) sccbtel i時(shí)序:2圖像數(shù)據(jù)輸出吋序:2.1 sccb 接 i i2-wire sccb functional block diagramk 6 sccb功能明sccb是歐姆尼圖像技術(shù)公“j (omnivision)開發(fā)的一種總線，并廣泛的應(yīng)用于0v系列関 悚代感器卜. sccbte 種3線的總線，它ftlsccb_e、sio_c、sio_dffl成，

11、/l:趵了w少引腳的芯 片i.維w為2根線.sio.c和si0jl2.2起始和終it時(shí)序start oftransmissionsccb_esio 一 c 一sin n 麵7 sccb 起始2013 2-21http：/ amfpga.taobao.com在啟動(dòng)傳轅過程中商m個(gè)時(shí)間參數(shù)，tpra和tprc, tprc披定義為siojdfs充電時(shí)問，這表 明siojd必項(xiàng)先于sccb_e披拉島的吋間，蝻小為15ns. tpra彼足銜r(shí)t： sio_d拉低之 « sioe披拉低的吋間，不能小p1.25us。數(shù)椒傳輸?shù)慕K|:stop ofra 8 sccb 終止fi ttpscsccbe

12、h升沿，sio_d保持邏軹卨電平的吋足小為15ns;tpsa是sio_d上升沿，sccb_e必須保持低電平的吋間，k小為ons.2. 3 sccb寫吋序?qū)憌序由3扣構(gòu)成.先寫s芥地址.再寫胄存器地址.最后巧袼存器的值，即id-address + $ub-addre» w-data. ov7670的沒格地址為0x42.敁后- p用來判斷冰芍.即it的時(shí)w為0x43.3-piase write transmission cyclephase 1 id address2013221http：/ amfpga.taobao.comphase 2 sub-address (3-ph«

13、»e write transmission)fflq sccb讀m傳輸吋序好次發(fā)送8個(gè)數(shù)你.sdat設(shè)？£為輸人.技收一個(gè)從機(jī)反饋的信v.依次發(fā)送id-address sub-address w-data 2. 4 sccb讀時(shí)序談1卜1序山 i 411 鉤成分別足 id address*sub-address+id address+read data »2.phase write transmission cycle2.phaw read tr.nimiwion cycto f9c vft| |tic addross|xtsubaddrou|x|(o a 紗m，

14、rod dau卜 4pbaw 1，一plwiw? phase 1phase 2丁冊屮特別捉刊.thtr« must be tither a 3-phase or a 2-phase vrrt參 transmission cycle asserted ahead of a 2-phase read transmission cycle. th© 2-phase read transmission cycle <see figure 3-7) has no to identify the sub-address. the 2-phase write transmissio

15、n cyde contains read date of 8 bits and a ninih donbcare bit or na bit. the master must drive the na bit at logical 1. 也就玷在read data環(huán)節(jié)里.有個(gè)na.即第9位要驅(qū)動(dòng)sio.d為髙電平。3. sccb 的 verilog 6!序解析if(wr)/i2c write: id-address + sub address + w-databegincase(sd_counter) /idle6*d0:beginsclk <= 1;i2cjit <= 1;9/2

16、5孑並術(shù)爻牦http:/ amfpga.taobao.com2013-2-21 ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; end <= 0;end/start6dl:beginsclk <= 1;i2c_bit <= 1;ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; end<= 0;end6 d2 :12c一bit <= 0;/i2c-sdat : 06 d3 : sclk <=

17、 0;/i2c_sclk = 0/slave addr-ack16'd4 :12c_bit <= i2c_wdata23】：6'ds : i2c.bit <= i2c_wdata22;/bit76 d6 :12c一bit <= i2c一wdatarl】；/bit66*d7 :12c一bit <= i2c一wdatai20】；/bh56'd8 :12c.bit <= i2c_wdata19;/bit46 d9 :12c.bit <= i2c_wdata|18;/bit36dl0 :12c一bit <= i2c_wda7a17;/b

18、it26*dll : i2c_bit<= i2c一wdata16i;/bill6*dl2 :i2c_bit<= 0;/high-z, input6dl3 : ackw1<= i2c-sdat:/ack16*dl4j2c 一 bit<= 0;/delay/sub addr-ack22013-2-21http:/ amfpga.taobao.com 6 dl5 :12c_bit <= i2cwdata15; /bit86 dl6 :12c_bit <= i2c_wdata14|; /bit76fdl7 :12c一bit <= i2c一wdata13;/bi

19、t611/236dl8:l2cbit<=i2cwdata12i;6dl9:l2cbit<=i2c 一 wdata11i;6*d20 :12cbit<=i2c.wdata1oj;6d21:l2cbit <= i2c.wdata9|;6 d22 :12c6 d23 :i2cbit <= i2c一wdata8|; /bitl/high-z, input6fd24: ackw2 <= i2c_sdat;/ack26d25:l2cbit<= 0;/delay/write data- ack36 d26 :12cit<= i2c_wda7a7; /bit86

20、 d27 :12cbit<= i2c_wdata6; /bit7 6'd28 :12c_bit<= i2c_wdata5|; /bit6 6'd29 :12c_bit <= i2c_wdata4; /bit56d30 :12c一bit <= i2c_wdata3j; /bit46 d31 :12cbit<= i2cwdata2|; /bit3 6'd32 :12c_bit <= i2c_wdata1); /bit26 d33 :12c_bit <= i2c_wdatao|; /bill6 d34 :12c-bit <= 0

21、;/high-z, input6*d35: ackw3 <= i2c_sdat; /ack3 6*d36:l2cbit<=0;/delay/stop6'd37 : begin sclk <- 0; i2c.bit <= 0; end 6d38:sclk <= 1;511*孑並術(shù)爻牦2013-2-21http:/ amfpga.taobao.com 6 d39 : begin i2cbit <= 1; end <= 1; end default: begin i2c_bit <= 1; sclk <= 1; end endcaseen

22、d/i2c read: id-ad dress + sub-address + id-address + r-data begincase(sd_counter)/idle6*d0:beginsclk <= 1;i2c 一 bit <= 1;ackw1 <= 1; ackw2 <= 1; ackw3 <= 1; ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; end <= 0;end/i2c readl: id-address sub-address/start6*dl:beginsclk <= 1; i2c_

23、bit <= 1;ackr1 <= 1; ackr2 <= 1; ackr3 <= 1; end <= 0;end6*d2 :12cjit <= 0;/i2c.sdat = 06 d3 : sclk <= 0;/i2csclk = 0/slave addr- ack16d4 :12c一bit <= i2c-wdata|23】： /bit8http:/ amfpga.taobao.com2013-2-21 6 d5 :12c一bit <= i2c一wdata|22】；/bit76 d6 :12c一bit <= i2c一wdata|21】

24、；/bit66fd7 :12c一bit <= i2c一wdata【20】：/bit56 d8 :12c一bit <= i2cwdata19);/bit46 d9 :12c一bit <= i2c一wdata|18b/blt36'dlo : i2c_bit<= i2c_wdaia17|;/bit26'dll : i2c_bit <= i2c_wdata16;/bitl6 dl2 :i2c_bit<= 0;/high-z, input6dl3 : ackr1<=i2c一sdat:/ack16'dl4:l2c_bit<= 0;/d

25、elay"sub addr- ack26*dl5 :12c一bit<= i2c一wdata15|;/bit86 dl6 :12cit<= i2c_wdata14;/bit76 dl7 :12c一bit<= i2c_wdata13|;/bit66'dl8 :12c_bit<= i2c_wdata12|;/bit56'dl9 :12c_bit <= i2c_wdata11;/bit46d20 :12c一bit <= i2c_wdata1o|;/bit36*d21 :12c一bit<= i2c一wdata9|;/blt26'

26、d22 :12c_bit <= i2c_wdata8j; /bitl6d23:l2c_bit<= 0;/high-z, input6 d24 : ackr2<= i2csdat;/ack26*d25:l2cbit<= 0;/delay/stop6'd26 : begin sclk <= 0; i2c_bit <= 0; end6*d27 : sclk <= 1;6 d28 : begin i2c一bit <= 1; /_end <= l;_/end孑並術(shù)爻牦2013-2-21http:/ amfpga.taobao.com /i2c

27、 read2: id-address + r-data> /start 6*d29: begini2c_bit<= 1;end6 d30 :12c bit <= 0;/i2c sdat = 06d31 :sclk<= 0;/i2c sclk = 0#/23/slave addr-ack36 d32 :12c-bit <= i2c 一 wdata23i;/bit86d33 :12cbit<=i2cwdata22;/bit76 d34 :12cbrr<=l2c_wdata 01】；/bit66*d35 :12cbit<=i2cwdata2o|;/bl

28、t56'd36 :12cbit<= i2c_wdata19|;/bit46'd37 :12cbit <= i2c_wdata18;"bit36 d38 :12cbit<=i2cwdata17);6d39 :12cbit<= lbl;/bltl read data6'd40 :12cbit <= 0;/high z, input6'd41: ackr3<= i2c_sdat;/ack36d42 :12c-_bit <= 0;/delayflag/read data-ack46*d43 :12c bit <=

29、/delay6vd44 :12c bit <« 0;/high-zz input6_d45 :12cdata7】<=i2c.sdat; /bit8 , input6*d46 :12c一rdata6| <= i2c一sdat;/bit7 , input2013-2-21孑並術(shù)爻牦http：/ amfpga.taobao.com6*d47 :12c一rdata51 <= i2csdat;/bit6，input6d48 :12c_rdata4 <= i2c_sdat;/bit5,input6d49 :12c一_ta3】<=i2c一sdat;/bit4,i

30、nput6*d50 :12c_rdata2】<=i2csdat;/bit3，input6d51 :12crdata1| <= i2c一sdat:/blt2,input6 d52 :12crdatao <= i2csdat;/bitlr input6*d53 :12cbit<= 1;/output /ack4 nack6 d54 :12c一bit<= 0;/delay/st 叩6 d55 : begin sclk <= 0; i2c一bit <= 0; end6 d56 : sclk <= 1;657 : begin i2c_bit <= 1

31、; end <= 1; end default: begin i2cjit <= 1; sclk <= 1; end endcaseendend4. ov7670/ « 位，vga，rgb565"rgb565, oo-ff(do) (yuv f要 /tslb(tslb3,上駁簾存器rtd罝佶總?cè)鏵set_ov7670 + 0: lut_data =16'hl204;(00:yuv,04:rgb)(8x 個(gè)位)set_ov7670 + 1 :lut_data=16'h40d0;改 01-fe(_set.ov7670 + 2 :lut.data

32、=16h3a04:comiaioijoouyv, 01:yvyu, 10:uyvy(cbycryl 11：vyuysetov7670 + 3: lut_data = lhadcsy/combttslbiab com13|0)00:yuyv,01:yvyu, 10:uyvy(cbycry|, 11:vyuyset_ov7670 + 4: lutdata =16_hle31;/默認(rèn) 01, bit水 f 拔悚 bit4】2013-2-21【義炎*孑並術(shù)爻牦http：/ amfpga.taobao.comft ft鏡像setjdv7670 + 5:lutdata=16fh6b00;/旁路pll倍頻：

33、oxoa：關(guān)w內(nèi)部 ld0： 0x00：打開 ld0set 一 ov7670 + 6:lutdata=16'h32b6;/href 檸制(80)set 一 ov7670 + 7:lut一data=16w713;/hstart輸出格式行頻開始髙8位(11|set_ov7670 + 8:lut_data=161801;/hstop輸出格式行頻結(jié)島 8 4(61|set_ov7670 + 9:lut-data=161902;/vstart輸出格八-場頻丌始fn'j 8 位(03|set_ov7670 + 10 :山 t一 data=16'hla7a;/vstop輸出格式場頻結(jié)

34、束辦8位(7b)set_ov7670 + 11 :山 t一 data=lhosoa;/vref幀s這力向控制（00>set-ov7670 + 12 :lut-data=16'h0c00;/dcw 使能禁止(00)set一ov7670 + 13 :lut_data=16.h3eoo;/pclk 分頻 00 normal. 10 (1分頻），11 （2分頻），12 （4分頻43<8分頻14 （16分頻set_ov7670 + 14 :lut_data=16*h7000;/00;normal, 80:移位 1, 00:彩條，80:漸變彩條set_ov7670 + 15 :lut_

35、data=167100；/00:normalf 00:移位 1, 80:彩條，80：漸變彩條set_ov7670 + 16 :lutdata=167211;/«認(rèn)水平，8抽樣（11）set_ov7670 + 17 :lutdata=16'h7300;/dsp縮放時(shí)鐘分故00 normal.10 （1分頻,11 （2分頻,12 <4 分頻,13 （8 分頻）14（16分頻）set_ov7670 + 18 :lut一data=163202;/默認(rèn)像疾始終址遲（02）set_ov7670 + 19 :lutdata=161180;/內(nèi)部1:作時(shí)鐘沒贊.良接使用外部時(shí)鐘源（80

36、>如何用w ov7670攝像頭20132-21jtlt孑並術(shù)爻牦http：/ amfpga.taobao.com1.判斷bi像義稅塊足否丄常i:作(m叫name.3rfw |doscription0apidr jproduct id number msb (read only)obi verr ii product id number ls8 (read only)1cmidh7f rmanufacturer id byte high (read only : ok7f)10midla2limanufacturer d byte low (read only : 0xa2)聞 10 ov

37、7670 product id 和 manufacturer id 寄存器通過讀収以上4個(gè)寄存器,將淡取的w通過10 口輸出si，或者在quartusii中用signaltapll logic analyzer 的/式米tft測是 ft i:作 il:常。alway>9c)lut data lut 二 w17a lot 二 wit* lut*wita省b.hoa, 8*h76> /pid s.hcb, 8fh73)j /ver 8bhlcr 8*h7f|； /hidh <8-hld, 8'ha2> /midlr帝名位識別號濃位識糸號 靄識灰；，-苓 廠商識故字爺

38、-飫oa5e(lut_ihdex) /audio coa£l9 d«ca /read eata index read mta 0 : readnkta 爭 1:readwita * 0 : read*t>ata 1 :2. 主盟、解磯lrtsnkisrtsuetsnmnunrtnnnullut-ummh 二lotuh 二 om lchwkta lvltazx tuttazh ivt:»ta lui'mia1ot*mtalot二 ulia lut:tataicteatilot wita lct_m?alotlotwitahwo，；hmoi；ebm3uh

39、bo! ehs2m/tad hocoo;*hte階 hooo; fc100;m3mj*ha?01;feuto;/utz. v». r3b5f$ (m!t77.0，m> <翼盆囑置3/rwssse g»-rr(au):xuv下s&w-nu卯>/t318(t3lb(3j, c(m3：0)o0:yuyv> 01:yvyu, 10:uy7t<cwtcrt> llsvyuy /cck>s|tslb：3f ccm13 0 > oolfwt mivyu, xoiayvy<oycm lltvyut /«認(rèn) blt(&#

40、187;水平鐿豫，blt|4)s重精徽人，,kpll«1i onu.關(guān)h!內(nèi)sldoi o«oo打fldo/助rr a*. cto>/.iutajc/vkaot 瑜&格jk場/*iro> 鬵t；»x場jrfl東萇eeiho/. v>m重方 ff s* i w>/ocwttn »-t(00>/kixfrboo horaal. |：0 cgs) .11，12 u分><分«x«/m：ncrmlr eo：«2l, 00: w><r 80:康變ft*/m：vor>al

41、v 00:21,so.旁變參條/軟認(rèn)*-羲直呼(u»人wftierj分um bona!. !c (1 分頻).11 (j分麟> 13 («分頻)，11 <1 分®m w (1<分頻> /軟認(rèn)景(m>/內(nèi)二繒置，18戈用外以上配s佶息足將ov7670 sk成卜面ka：1) vga 分辨申.rgb565 isa2) 水鏡像3j關(guān)閉pll.直接使用外部時(shí)鐘，打開ldo,使用內(nèi)部電源4 )pclk正常模式，不分頻,xclk = pclksmb1彩條vga接ii時(shí)斤:如卜：is/232013-2-21jtlt孑並術(shù)爻牦http：/ amfpga

42、.taobao.comrowo row1 row 2row 479note: forrwrdu.bt f«yuvfrgb.t,s2xlmahran vga輸出時(shí)呼ra計(jì)算pclk的參數(shù)，如下所示：vsync： 510* line = 3*tline + 17*tline +480*tline+10*tline href： 784*tp = 610*tp + 144*tphsync： 784*tp = 80*tp + 4o*tp + 640*tp + 19*tp vga rgb565, yuv 30fps：pclk = 784 * 510 * 30 * 2 (byte) = 23990

43、100 = 24mhz 簡單的說0v7670圖像的時(shí)序跟vga時(shí)序詐常甫m，只不過vga時(shí)序是ppga溢要主 動(dòng)產(chǎn)生的，lfuov7670時(shí)什足!:動(dòng)輸出的。這芯戲我們根則閻定的時(shí)序，來準(zhǔn)確接 收毎一個(gè)像索的數(shù)樅。以卜是rgb565的ov767o招像頭的閣像時(shí)序i禮pclk是連 紱的，每一行分行有效信每-場有場燈效信號，在場有效信兮開始，第一個(gè)行有效信號的第一個(gè)數(shù)據(jù)便是第一個(gè)像素的尚八位數(shù)據(jù)。每一個(gè);象素 邊分兩次送。17/232013221【發(fā)憂電孑放術(shù)爻http：/ amfpga.taobao.comhreftnrprln_nn_r|_r一匚(row data)figure 11 rgb

44、568 output timing diagram12 0v7670輸出rgb565數(shù)據(jù)格式此處耑嬰il:意的坫，pclk坫什迮續(xù)輸出脈沖足坷以妃咒的，寄存器如卜所品15com1000rwcommon control 10brt(7 reservedbit6href changes to hsyncb<(5pclk output option0 free rurmlnq pclk1 pclk does not toggle during hortzontai blarik m4 pclk reverse唎w【2jbm【1】href reverse vsyncopdor0: vsync c

45、nanges on tailing edge of pclk1 vsync changes on rrsmg edge of pclk vsync negativehsync negative閿13 com1o寄存器w認(rèn)bit5沒成0.則-h輸出pclk。此處©又注pcls的few足，在fpga杓序該 収指像頭數(shù)裾時(shí).程序時(shí)鐘足pclk卯動(dòng).所以一般設(shè)k成一打"脈沖輸出.在rgb565輸出吋序中，href 融 f時(shí)閣像數(shù)據(jù)有效，此時(shí)fpga可以在pclk上升沿談取8 <4困像數(shù)據(jù)。klflj羅列卜則href相關(guān)的«介器功能:20132211義星電孑叢術(shù)爻ht

46、tp：/ amfpga.taobao.comofcom643rwcommon control 6&u7): output d opxai duck line option 0 dfsjue href at optical mack i: enawe href at opocai wack &t(67 reserved reset jl bmiig when fomut changes 0: no reset1： resets im«g biqoj:reserved3cc0m1268rwcommon contol 12brt(71 href option0: no hr

47、ef *fien vsync is low 1: always has href bfl(eo r«cfv«j3. sk 結(jié)！經(jīng)過t述設(shè)置后，得到卜述vga rgb565的輸出時(shí)序。232/21 its34 的閣14 rgb565輸出邏軹分析波形4. fpgait:取0v7670攝像頭輸出數(shù)裾1）模塊輸入輸出在開發(fā)板提供的程序屮,cmos.capture.v投塊對祖像炙數(shù)據(jù)進(jìn)行采染_ 先6 fw塊的輸入輸出：212z2324 noduie cmoscaptuxe </global clockxclk,"2sku25-rpuclrst_nr2621/i2c i

48、nltillzedone28inputimt_done#/ibit done2930/seasox znexf毳c會31outputcmcs rsi lb/»c3 voxk state (5ms delay for sccfc config)32outputcmc3_pvdn,/cncs power on33ou;pucoicsxj：,"2smu34inputcucsyzlk,/2shhz35lfipuc(?!0)atcs-idwa,/ckos dara36incucchc3:vs¥!ic,/l: valid37.nputo4c3:hrzr,/»: va

49、xld9b39z/cuput j雪nsozdata40output regcmos oclk#"l/i pclk41output reg (15:0) cmos 二。nita,z/kbits rgb42 0output xegcmos 二valid,/baca enable43output seg p:d cmc3:fp3-»7*"cxkj4420132-211發(fā)憂電孑並術(shù)爻牦http：/ amfpga.taobao.com主要的輸入fd b ri ov7670輸出的ra像s據(jù)信卩，it時(shí)汴如fffl：cmos.capture.v模塊輸出時(shí)屮如krb25/23re

50、屮第一張閣足一行w®數(shù)據(jù)，卜而w張足對起點(diǎn)和終點(diǎn)的放人i禮從閣屮可以n釕出, 一行數(shù)據(jù)總共足5120/8=640,即-行有640個(gè)數(shù)i.述計(jì)算v.lfti 8指的足一個(gè)cmos_oclk脈沖寬度。從卜可以ft出.cmos-oclk的下降沿?cái)?shù)據(jù)穩(wěn)定.因此cmos captures的f續(xù)連接模塊呵以通u cmos.oclk的卜降沿鎖存數(shù)煙*2）模塊總體框衆(zhòng)re ®cmc3 vsyne：always (pcsede smospcuc ox uegedoe imtjo oeainxfdxmtm) ibcmc5_v5yn: < 1； else -»cmcs_v5ync

51、 <- cmosvsymcf"場訇歩：嚷電平賓農(nóng)ndwin qms vsyhc pvwr (scx03jwxc,0«03j/stbe 3*b01) ? l*bl : l*bo;/vstjk上尹沿琺東檢# vsync信卜.升沿。cmos一vsyncjwer w v個(gè)商電平脈沖輸出念味者-幀數(shù)據(jù)。該ft號用j對賄幀進(jìn)行計(jì)數(shù)，在h面模塊里面用到*2013 2 21【發(fā)憂電孑並術(shù)爻rthttp：/ amfpga.taobao.comlie149150151152153154155154157158169 i«oo141 1«2163 1« us

52、1«4168 im170171170 1” 17，/-/waie for sensor ouepux data valid, reg (3:0) framecontjr<9rsumvaxid;alwa/93ipcaeoge cmospglk or cegeage5be9iaif (jlrsrnis»e«isfranecont < 0; franevalld < 0; endelse if(init_done>i£ (cxosvsxhcqvex lfbl>smglir(fratmwcont < 10)eb«9a

53、nfraecontfra»«2vaxld < l*b0; nd1"sbeginfra»e_cent <- frawecont;fraae.valxd < lfbl:"1!1揭_出有效endend end1rst si/cmos 12c初始化充fxaxe cont l*bi;end此處進(jìn)行10 m計(jì)數(shù),當(dāng)計(jì)數(shù)到時(shí)輪出frame.valid信號離電平存效。因?yàn)橹蟛⑽磳?frame_cont進(jìn)行淸本，所以當(dāng)frame.valid變?yōu)閰l后，一克保持島電f不變。此處為什么耍 這么做，is?l ov7670數(shù)據(jù)t冊page6的說明，布存器sfflwg （即，上閣158行l(wèi)nit_done 信號有效,需要至少等待10幀。faki# clkt resety) input cloch frequencymhzkukinput clocfc pwod21 ；42100nstax occtocfcoutycyd*455055%hvsett*ne after softwaw如ord*we rw«t1ts«gsettling hme for register c