電子設(shè)計(jì)自動(dòng)化I隨堂練習(xí)答案

1、電子設(shè)計(jì)自動(dòng)化I隨堂練習(xí)答案第6章VHDL結(jié)構(gòu)與要素1.實(shí)體下列實(shí)體的語(yǔ)句結(jié)構(gòu)是否正確,如果不正確,請(qǐng)指出具體錯(cuò)誤。(1ENTITY mux21 ISPORT(a, b: IN BIT;s: IN BIT;y: OUT BIT;END mux21正確(2ENTITY mux21 ISPORT(a ,b: IN BIT;s: IN BIT;y: OUT BIT;END ENTITY不正確,“END ENTITY mux21”(3entity MUX21 isport(A, B: in bit;S: in bit;Y: out bit;end mux21正確(4ENTITY mux21 ISPOR

2、T(a, b: IN BIT; -a和b分別是數(shù)據(jù)輸入端s: IN BIT;y: OUT BIT;END ENTITY mux21正確(5ENTITY mcu16 ISGENERIC(addrwidth: INTEGER:=16;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16正確(6ENTITY mcu8 ISGENERIC(addrwidth: INTEGER:=16;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu8正確(7ENT

3、ITY mcu16 ISGENERIC(addrwidth: INTEGER;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16正確(8ENTITY mcu16 ISGENERIC(addrwidth:=16;PORT(add_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16錯(cuò)誤,“GENERIC(addrwidth: INTEGER:=16;“(9ENTITY mcu16 ISGENERIC(addrwidth: INTEGER:=16;PORT(a

4、dd_bus: OUT STD_LOGIC_VECTOR(addrwidth-1 DOWNTO 0;END mcu16錯(cuò)誤,“GENERIC(addrwidth: INTEGER:=16;“(10ENTITY nand2 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;PORT(a, b: IN STD_LOGIC;c: OUT STD_LOGIC;END nand2正確(11ENTITY gate4 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;PORT(a: IN STD_LOGIC;c: OUT STD_LOG

5、IC;d: INOUT STD_LOGIC;e: BUFFER STD_LOGIC;END gate4正確(12ENTITY nand2 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;PORT(a, b: IN trise;c: OUT tfall;END nand2錯(cuò)誤,trise和tfall不是數(shù)據(jù)類型(13ENTITY nand2 ISGENERIC(trise: TIME:=1ns;tfall:TIME:=1ns;END nand2錯(cuò)誤,實(shí)體的語(yǔ)句結(jié)構(gòu)必須包含端口說明2.求下列以數(shù)制基數(shù)表示的文字的十進(jìn)制數(shù)值16#F.11#E2 15x162+1

6、x161+1x160=38578#167.2#E1 1x83+6x82+7x81+2x80=9542#10.0001_1111#E8 1x29+1x24+1x23+1x22+1x21+1x20=543 3.判斷下列文字或標(biāo)識(shí)符是否合法“2FFT”合法10#1A# 不合法O"1A”不合法X#E#E2 合法ELSE 不合法Not$ack 不合法_june 不合法june_ 不合法june_ _1 不合法A or B 合法/A or B/ 不合法AB 不合法A/B 合法Enter 合法“1_1101_1000”合法4.數(shù)據(jù)類型根據(jù)要求定義下列常量(CONSTANT、變量(VARIABLE或

7、信號(hào)(SIGNALTTL高電平5V,TTL低電平0VCONSTANT TTL_H: REAL:=5.0;CONSTANT TTL_L: REAL:=0.0;a大于b結(jié)果為真,a小于b結(jié)果為假CONSTANT a_gt_b: BOOLEAN:=TRUE;CONSTANT a_lt_b: BOOLEAN:=FALSE;程序編寫者xiaomingCONSTANT editor: STRING:=“xiaoming”;xiaoming的學(xué)號(hào)201302031111CONSTANT xiaoming_xuehao: STRING:=“201302031111”;xiaoming的EDA考試成績(jī)90分CO

8、NSTANT xiaoming_chengji: INTEGER:=90;8位二進(jìn)制表示的最大十進(jìn)制數(shù)CONSTANT 8octect_to_integer: INTEGER:=255;用于LED七段碼顯示數(shù)字“9”CONSTANT num_9: BIT_VECTOR:=”1111011”;3-8譯碼器的輸入信號(hào)SIGNAL oct_decoder_input: BIT_VECTOR(2 downto 0;D觸發(fā)器輸出信號(hào)SIGNAL D_trigger_output: STD_LOGIC;5.賦值語(yǔ)句根據(jù)要求給下列變量(VARIABLE或信號(hào)(SIGNAL賦值面積a等于a:=3.14*r*r

9、;給8位位矢量的高4位賦值1a(7 downto 4:=”1111”;給8位位矢量的奇數(shù)位賦值1a(7:=”1”;a(5:=”1”;a(3:=”1”;a(1:=”1”;開關(guān)量信號(hào)初值為低電平SIGNAL switch_signal: BIT:=0;EDA考試第一名成績(jī)是99分eda_chengji_1 := 99.0;EDA考試第一名的學(xué)號(hào)是201302031111eda_xuehao_1 := “201302031111”;負(fù)反饋電路信號(hào)nf給信號(hào)y賦值,傳輸延遲10nsy<=nf AFTER 10 ns;用變量a給信號(hào)y賦值y <=a;將信號(hào)y定義為標(biāo)準(zhǔn)邏輯位類型并設(shè)置為未初始

10、化的SIGNAL y: STD_LOGIC:=U;6.順序語(yǔ)句(1根據(jù)電路補(bǔ)充VHDL語(yǔ)句ab (aSIGNAL a, b, z: BIT; PROCESS(a, bBEGINIF(a= 0 THENz<=a;ELSIF( b=0 THEN z<=a;ELSEz<=b;END IF;END PROCESS;a b(bSIGNAL a, b, z: BIT; PROCESS(a, bBEGINIF( a = 1 THENz<=1;ELSIF( b = 0 THEN z<=1;ELSEz<=0;END IF;END PROCESS; (cSIGNAL a, b,

11、 c, z: BIT;PROCESS(a, b, cs<= a&b&c ;BEGINCASE s ISWHEN “111 ”=>z<= 1 WHEN OTHERS =>z<=0 END CASE;END PROCESS; (dSIGNAL a, b, c, z: BIT;PROCESS(a, b, cs=a&b&cBEGINCASE s ISWHEN “ 000”|”011”|”101”|”110”=>z<= 0 WHEN OTHERS =>z<= 1 END CASE;END PROCESS;(2根據(jù)功能要

12、求寫出語(yǔ)句a8位比較器SIGNAL a,b: BIT_VECTOR(7 DOWNTO 0;SIGNAL a_more_or_equal_to_b: BOOLEAN;_a_more_or_equal_to_b <= FALSE;FOR n IN 7 downto 0 LOOPIF( a(n < b(n THENa_more_or_equal_to_b <= FALSE;EXIT;ELSIF( a(n >= b(n THENa_more_or_equal_to_b <= TRUE;EXIT;ELSENULL;END IF;END LOOP;(3根據(jù)語(yǔ)句回答問題a(0

13、to 7:=”UUUUUUUU”;b(0 to 15:=” UUUUUUUUUUUUUUUU”;L_x: FOR n IN 0 TO 7 LOOPa(n:=0;k:=0;L_y: LOOPb(k:=0;NEXT L_x WHEN(k>=n;b(k+8:=0;k:=k+1;END LOOP L_y;END LOOP L_x;問上述語(yǔ)句運(yùn)行結(jié)束后變量a和b的值?a(0 to 7:=”00000000”;b(0 to 15:=” 0000000”;7.并行語(yǔ)句(1用并行信號(hào)賦值語(yǔ)句改造下列順序語(yǔ)句 b(aARCHITECTURE a_and_not_b OF mux21 IS SIGNAL a

14、, b, z: BIT;BEGINz<=a WHEN a=0ELSEa WHEN b=0ELSEb;END a_and_not_b; (bARCHITECTURE a_xor_b_xor_c OF xor31 IS SIGNAL a, b, c, z: BIT;BEGINs =a&b&c;WITH s SELECTz<=0WHEN “000”,0WHEN “011”,0WHEN “101”,0WHEN “110”,1WHEN OTHERS ;END a_xor_b_xor_c;(2補(bǔ)充元件例化部分語(yǔ)句實(shí)現(xiàn)電路功能 ENTITY or2 ISPORT(a, b: IN BIT;c: out BIT;END or2;ARCHITECTURE or2behv OF or2 ISBEGINc<=a or b;END or2behv;ENTITY or62 ISPORT(a1, b1, a2, b2, a3, b3: IN BIT;z1, z2: out BIT;END or62;ARCHITECTURE or62behv OF or62 ISCOMPONENT or2PORT(a, b: IN BIT;c: out BIT;END COMPON