數(shù)模混合仿真基本流程.

1、數(shù)/模混合仿真基本步驟1、 輸入命令“ which verilog.vmx參看仿，真所需的“ verilog.vmx文件是否存在,“which icfb查看所需的系統(tǒng)文件是否存在；2、 在需要進(jìn)行仿真的文件目錄下啟動(dòng)icfb ,將系統(tǒng)中模擬電路部分電路結(jié)構(gòu)做成symbol ,數(shù)字電路部分用verilog編寫,做成view名稱為“ functional的模塊;3、除了有 schematic view 之夕卜，增力卩 config view :library man ager file new cell view 如圖填寫后，點(diǎn)擊ok彈出對(duì)話框點(diǎn)擊use template彈出對(duì)話框Create N

2、ew FileM戶勺詁irAtlnn在 name選項(xiàng)中選擇 spectreVerilog，點(diǎn)擊 ok，關(guān)閉 new configuration 對(duì)話框，在 new configuration對(duì)話框中，將 view 名稱改為 schematic如圖f啊ieh梓EdlToi: Mew Confl guytionFill- Edit VI«WPIi-Ihs H»l«(CP f 專 C "學(xué)Tap CjpIILdbnry: faikj曹Ctll:(QuC5iaCcSwQ5Z view:駅祜“頁(yè)openGloba I Hindi 莎驚Lbhery I i霉r?斤幣

3、T託View LiiLftdafiuifiSttp LrvLptclrt splfit"virlIciW<i?liftc*vn罰i ri如你Ob>ict: adc_iw.cut_qidk:_cwiv_t2_»x(mVirw) pedb pith camrwrt b« hoxsadFailed c<in p9f¥Ht-child 曲嵋b#i* for 血艸臥fkKp ady.flltlrs OFF保存后關(guān)閉對(duì)話框4、開始仿真時(shí)關(guān)閉雙擊config ,彈出對(duì)話框Cadence® hierarchy editor： New Conf

4、igurationFile Ed it ViewPlu<"KcS H膾他 c欝區(qū)冒富Top CellLibrary; |adc_sar Cell： |cut_qadc_conv_t25_xx View： |scherraticGlobal Bindings般按照默認(rèn)值，只顯示schematic不顯示con fig ,點(diǎn)擊ok5、在彈出的 schematic對(duì)話框中，tool analog environment set upsimulator/directory/host，彈出對(duì)話框Hchoosing Simulator/Directory/Host - Afflrma Ana

5、log Circuit DesiOKCancelDefaultsHelpSimulatorspectreVerilogProject DirectorysuwulatioiHost Mode local remote n distributed吸t鞘s?擇欝曲橋;MryDigital Host Mode localremote將 simulator 改為如圖,ok ; schematic中將出現(xiàn) mixed signal選項(xiàng)，點(diǎn)擊該選項(xiàng),下拉菜單中出現(xiàn)三個(gè)選項(xiàng),其中display partition選項(xiàng)中可選擇顯示模擬信號(hào)線數(shù)字信號(hào)線、或混合信號(hào)線;in terface eleme nts選項(xiàng)中的library選項(xiàng)，應(yīng)根據(jù)工藝條件與設(shè)計(jì)要求填寫相關(guān)的A D、D A相關(guān)信息，如信號(hào)上升、下降時(shí)間，模擬信號(hào)向 數(shù)字信號(hào)轉(zhuǎn)換的高 低電平等；6 填寫完畢后關(guān)閉該對(duì)話框