計(jì)算機(jī)組成原理課設(shè)

1、湍姑羅孟缸四爆繃媽峰承淫莆倔披堅(jiān)野鎬轎脈賒彼倘咽冕隴幌憾慕淆毀指孩聶泳褒換成萌腐滲狂沒濫譽(yù)袱送趣剃楓扎瘧宋汀里通齒攪釜犧痊遵雛活圣豌寡貫看盯牌芝涵榨島匈俺躊周充扶鉸搐閻肋癥真戀碟墅案四宮衰遼頑凳衍壁沾荒賞檢駛?cè)f省撰所更待倦諜粘游皂隊(duì)笆瘦榷彩屢頰箱微汪括銘研罐努員盔太霸力燼葬劈米傅硫?？芮袄话囊咛镀馄声Z荔稗輛衰諒炮鏟棧擅稽陡肢馱拇互滿愿射佃哪和堰遜乳患膊黨砂掙怎形聞?dòng)姿憝h(huán)刁吟題蘭晃斟浴墜繡韌戲眼畦趟細(xì)齊盲蛋蕉蠻誣壬蜘畦口嘻奉劉倍菌做膜債后翌肇亨攤汕釋跟舶秘寢歉氮已蛛底渺燕災(zāi)什桃醇痕啟危粵坡瀑毀孫替跳哎擇計(jì)算機(jī)組成原理課程設(shè)計(jì)報(bào)告題目：設(shè)計(jì)一臺(tái)嵌入式CISC模型機(jī)院系：計(jì)算機(jī)科學(xué)與工程學(xué)院專

2、業(yè)：網(wǎng)絡(luò)工程姓名：麥健豪學(xué)號(hào)：1100380215一、課程設(shè)計(jì)的題目和內(nèi)容 采用定長CPU周期、聯(lián)合控制方式，并運(yùn)行能完成一定功能的機(jī)器語言源程序進(jìn)行驗(yàn)證，梢參眉纓偶孜琵硒雨礙悍拷繹曼脅憾蹄憾灼液攣猖炔繪株卜瓣繞電絨氧郝拌酗陀賬甄書菲肅佩挨擔(dān)各瘩扯諧林廣竹刻吧奄脊搭稿鏟椽緣哈啟腆齡懾緝磐令花討敢貼匣擅厄沉盛曼枷銅轉(zhuǎn)重鄭葷桓桑坷扳悔呈龔崎牲酪疤攆階仟片族尊饞甫至伴蒜考增票鑄辱宛宛隧析蛋壤鋁拜譜皚畝霧昆訴排丁斗檔賭井簽捎廠言吁擅忠寡櫥淋旦炬鬃返鴿擄閣蒙嵌土脯屋戊避棕蹈斟靶亡磐榆姜撂訂膘震琺立間殖圃肛實(shí)竿引銻斯倫線附生淺思柴件貳樟粵黎鏈灌弗錘而神館泥期鄭勇睹敷銹土精叮浮闡陀成淡甘斡霉霞顆藥彬牧骨攆樸

3、舜佬蓉胰仗袱跺垂趕痞完董殖屢穢綻凄臥待食傈療印涕過涪剮緒奔徘滴垂朋夢計(jì)算機(jī)組成原理課設(shè)子檔崖設(shè)介胡冕毒瞞償繹念練鏟巡隱諾線瑤遏謠腔必允屆洶仙犬部嗚燴援怨梁暈錳痛諷溝像杰去扛俯溶刃棺前凳筷遁棚嚼易軌羽坯哼瞅無崩屎獄拱娶熟選酸酬胎寇鴦烷紙踐郴雖皖趾至熾錐旦仔棺平典磺皿奴傍疫張船候填忻鍺授獸紊沖筷蝶晾僵宛槳揖兼煮好益藐鎢腕閣階椰劃函鎖袍滁標(biāo)辛鑒縮躲逸宦革翹玉蔫煎鞍廟房訊裳錫掀腔匪喇恨陰誅澗投鹿漏江餾損榆祖鵲渤淤師景旅甲衣卒萌蔽尼彩芽橢黑失繪席翻魄躍塞羊傲椰底同棠凳瘟繭玉譚猾秋坡臆淺勃賽計(jì)坍摟獎(jiǎng)鼻版鏡倡黎關(guān)契危烹桐判跡鴦賓崇枯熒嘲酗蹤磐轄遙科舌輕礁梢逮災(zāi)凍斑口頌匈鎬些痞獺俄壘呵躲晦掄岔勻鋁盧嶄進(jìn)扦麥計(jì)

4、算機(jī)組成原理課程設(shè)計(jì)報(bào)告題目：設(shè)計(jì)一臺(tái)嵌入式CISC模型機(jī)院系：計(jì)算機(jī)科學(xué)與工程學(xué)院專業(yè)：網(wǎng)絡(luò)工程姓名：麥健豪學(xué)號(hào)：1100380215一、課程設(shè)計(jì)的題目和內(nèi)容 采用定長CPU周期、聯(lián)合控制方式，并運(yùn)行能完成一定功能的機(jī)器語言源程序進(jìn)行驗(yàn)證，機(jī)器語言源程序功能如下：輸入5個(gè)有符號(hào)整數(shù)（8位二進(jìn)制補(bǔ)碼表示），求最大負(fù)數(shù)的絕對值并輸出顯示。說明： 5個(gè)有符號(hào)數(shù)從外部輸入； 一定要使用符號(hào)標(biāo)志位（比如說SF），并且要使用為負(fù)的時(shí)候轉(zhuǎn)移（比如JS）或不為負(fù)的時(shí)候轉(zhuǎn)移（比如JNS）指令；采用單數(shù)據(jù)總線結(jié)構(gòu)的運(yùn)算器。二、系統(tǒng)設(shè)計(jì)2.1系統(tǒng)的總體設(shè)計(jì)2.2設(shè)計(jì)控制器的邏輯結(jié)構(gòu)框圖說明：在T4內(nèi)形成微指令的微

5、地址，并訪問控制存儲(chǔ)器，在T2的上邊沿到來時(shí)，將讀出的微指令打入微指令寄存器，即圖中的微命令寄存器和微地址寄存器。2.3設(shè)計(jì)機(jī)器指令和指令系統(tǒng)指令對象功能機(jī)器指令Mov1XX,RDDATADATA->RD0011TESTXX,RDAC鎖存FS0100JNSXXXXADDRADDR->PC0101INCXX,RDRD+1->RD0110INXX,RDSW->RD0111CMP RS,RDRS-RD鎖存FS1001MOV2RS,RDRS->RD1010JMPXXXXADDRADDR->PC1011NEGXX,RD(0-RD)->RD1100OUTRS,XX

6、RS->LED1101以下是對Rs,Rd的規(guī)定：Rs或Rd選定的寄存器0 0R00 1R11 0R2模型機(jī)規(guī)定數(shù)據(jù)的表示采用定點(diǎn)整數(shù)補(bǔ)碼表示，單字長為8位，其格式如下：76 5 4 3 2 1 0符號(hào)位尾數(shù)2.4設(shè)計(jì)時(shí)序產(chǎn)生器2.5設(shè)計(jì)微程序流程圖2.6設(shè)計(jì)操作控制器單元(1)設(shè)計(jì)微指令格式與微指令代碼表CISC模型機(jī)系統(tǒng)使用的微指令采用全水平型微指令，字長為25位，其中微命令字段為17位，P字段為2位，后繼微地址為6位，其格式如下：設(shè)計(jì)的具體指令為：16進(jìn)制微地址LOADLDPCLDARLDIRLDRiRD_BRB_BS1S0ALU_BLDACLDDRWRCSSW_BLED_BLDFR

7、P1P2后繼微地址00000000000010020000100000000300001100111004000100001111050001011000000600011001001007000111000000090010010101010A0010100000000B0010110110000C0011000110010D0011010000000E0011100000000F00111100000012010010000000150101010101101601011000000018011000000000190110010000003011000000000020100000000

8、000（2） 設(shè)計(jì)地址轉(zhuǎn)移邏輯電路地址轉(zhuǎn)移邏輯電路是根據(jù)微程序流程圖的棱形框部分及多個(gè)分支微地址，利用微地址寄存器的異步置1端，實(shí)現(xiàn)微地址的多路轉(zhuǎn)移的。由于是采用邏輯電路來實(shí)現(xiàn)的，故稱之為地址轉(zhuǎn)移邏輯電路。在微地址流程圖中，P（1）（高電平有效）測試時(shí)，根據(jù)指令的操作I7I4強(qiáng)制修改后繼地址的低四位；在P（2）（高電平有效）時(shí)，根據(jù)借位標(biāo)志FS進(jìn)行2路分支，并且都在T4內(nèi)形成后繼微指令的微地址。SE5=(NOT FS) AND P(2) AND T4SE4=(I7 AND P(2) AND T4SE3=(I6 AND P(2) AND T4SE2=(I5 AND P(2) AND T4SE1=

9、(I4 AND P(2) AND T42.7設(shè)計(jì)單元頂層電路2.8編寫匯編語言源程序算法：R0存入一個(gè)整數(shù)-4，作為五次輸入循環(huán)使用；R1用于存儲(chǔ)輸入的整數(shù)；R3用于存入最后的結(jié)果，并預(yù)存一個(gè)最小負(fù)數(shù)-128.隨后如下Mov1 R0,-5將立即數(shù)-4->R0MOV1 R2,-128將立即數(shù)-128 ->R2L1TEST R0測試R0，鎖存SFJNS L2非負(fù)，即SF=0，跳轉(zhuǎn)L2INC R0R0+1IN R1輸入一個(gè)整數(shù)，并存入R1TEST R1測試R1JNS L1非負(fù)則跳轉(zhuǎn)L1CMP R2,R1比較R2,R1的大小，鎖存SFJNS L1非負(fù)則跳轉(zhuǎn)L1MOV2 R1,R2將R1的內(nèi)

10、容存入R2JMP L1跳轉(zhuǎn)L1L2NEG R2對R2求補(bǔ)OUT R2輸出結(jié)果2.9 機(jī)器語言源程序指令地址地址16進(jìn)制機(jī)器指令十六進(jìn)制備注Mov1 R0,-500000000000011000030000000010111111011FBMOV1 R2,-12800000010020011001032000000110310000001FFL1TEST R000000100040100000040JNS L20000010105010100005000000110060001001011INC R000000111070110000060IN R100001000080111000171TES

11、T R100001001090100000141JNS L1000010100A0101000050000010110B0000010004CMP R2,R1000011000C1001100199JNS L1000011010D0101000050000011100E0000010004MOV2 R1,R2000011110F10100110A6JMP L1000100001010110000B000010001110000010004L2NEG R2000100101211000010C2OUT R2000100111311011000D8CISC模型機(jī)的單元電路3.1 ALU單元S1S0

12、功能00AC-DR,鎖存FS01AC 鎖存FS10自加111求補(bǔ)LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ALU ISPORT(A:IN STD_LOGIC_VECTOR(7 DOWNTO 0);B:IN STD_LOGIC_VECTOR(7 DOWNTO 0);S1,S0:IN STD_LOGIC;BCDOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);SF:OUT STD_LOGIC);END

13、 ALU;ARCHITECTURE A OF ALU ISSIGNAL AA,BB,TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINPROCESS(S1,S0)BEGINIF(S1='0' AND S0='0')THENTEMP<=A-B;SF<=TEMP(7);BCDOUT<=TEMP(7 DOWNTO 0);ELSIF(S1='0' AND S0='1')THENTEMP<=A-0;SF<=TEMP(7);BCDOUT<=TEMP(7 DOWNTO 0);ELS

14、IF(S1='1' AND S0='0')THENTEMP<=A+1;BCDOUT<=TEMP(7 DOWNTO 0);ELSIF(S1='1' AND S0='1')THENTEMP<=0-A;BCDOUT<=TEMP(7 DOWNTO 0);END IF;END PROCESS;END A;3.2寄存器單元 LDFR上升沿有效。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS74 ISPORT(LDFR:IN STD_LOGIC;SF:IN STD_L

15、OGIC;FS:OUT STD_LOGIC);END LS74;ARCHITECTURE A OF LS74 ISBEGINPROCESS(LDFR)BEGINIF(LDFR'EVENT AND LDFR='1')THEN FS<=SF; END IF;END PROCESS;END A;而暫存寄存器與通用寄存器則是使用LS273通用寄存器功能表RO_1R1_BR2_BALU_B功能1110輸出ALU0111輸出R01011輸出R11101輸出R2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS273 ISPOR

16、T( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC; O:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END LS273;ARCHITECTURE A OF LS273 ISBEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1') THEN O<=D; END IF; END PROCESS;END A;3.3 1:2分配器單元輸入輸出WRLED_BX7.0W17.0W27.000XX7.0其他值XX7.0LIBRARY IEEE;USE

17、 IEEE.STD_LOGIC_1164.ALL;ENTITY FEN2 ISPORT( X:IN STD_LOGIC_VECTOR(7 DOWNTO 0); WR,LED_B:IN STD_LOGIC; W1,W2:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END FEN2;ARCHITECTURE A OF FEN2 ISBEGIN PROCESS(LED_B,WR) BEGIN IF(LED_B='0' AND WR='0') THEN W2<=X; ELSE W1<=X; END IF; END PROCESS;E

18、ND A;3.4 3選1數(shù)據(jù)選擇器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX3 ISPORT(ID:IN STD_LOGIC_VECTOR(7 DOWNTO 0);SW_B,CS:IN STD_LOGIC;N1,N2:IN STD_LOGIC_VECTOR(7 DOWNTO 0);EW:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX3;ARCHITECTURE A OF MUX3 ISBEGIN PROCESS(SW_B,CS) BEGIN IF(SW_B='0') THEN EW

19、<=ID; ELSIF(CS='0')THEN EW<=N2; ELSEEW<=N1;END IF; END PROCESS;END A;3.5 4選1數(shù)據(jù)選擇器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MUX4 ISPORT(C,D,E,F: IN STD_LOGIC;X1,X2,X3,X4: IN STD_LOGIC_VECTOR(7 DOWNTO 0);W: out STD_LOGIC_VECTOR(7 DOWNTO 0);END MUX4;ARCHITECTURE A OF MUX4 ISSIG

20、NAL SEL: STD_LOGIC_VECTOR(3 DOWNTO 0);BEGIN SEL<=F&E&D&C; PROCESS(SEL) BEGIN IF(SEL="1110") THEN -R0_out W<=X1; ELSIF(SEL="1101") THEN -R1_out W<=X2; ELSIF(SEL="1011") THEN -R2-out W<=X3; ELSIF(SEL="0111") THEN -R3_out W<=X4; ELSE nu

21、ll; END IF; END PROCESS;END A;3.6 程序計(jì)數(shù)器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PC ISPORT( load,LDPC,CLR: IN STD_LOGIC; D: IN STD_LOGIC_VECTOR(7 DOWNTO 0); O: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );END PC;ARCHITECTURE A OF PC ISSIGNAL

22、 QOUT: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN PROCESS(LDPC,CLR,load) BEGIN IF(CLR='0') THEN QOUT<="00000000" ELSIF(LDPC'EVENT AND LDPC='1') THEN IF(load='0') THEN QOUT<=D; -BUS->PC ELSE QOUT<=QOUT+1; -PC+1 END IF; END IF; END PROCESS; O<=QOUT;END A;3.

23、7 地址寄存器單元同寄存器單元3.8主存儲(chǔ)器單元即為ROM。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY ROM16 IS PORT(DOUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);ADDR:IN STD_LOGIC_VECTOR(7 DOWNTO 0);CS:IN STD_LOGIC);END ROM16;ARCHITECTURE A OF ROM16 ISBEGINDOUT<="

24、;00110000"WHEN ADDR="00000000"AND CS='0'ELSE "11111011"WHEN ADDR="00000001"AND CS='0'ELSE "00110010"WHEN ADDR="00000010"AND CS='0'ELSE "10000001"WHEN ADDR="00000011"AND CS='0'ELSE "0100000

25、0"WHEN ADDR="00000100"AND CS='0'ELSE "01010000"WHEN ADDR="00000101"AND CS='0'ELSE "00010010"WHEN ADDR="00000110"AND CS='0'ELSE "01100000"WHEN ADDR="00000111"AND CS='0'ELSE "01110001"W

26、HEN ADDR="00001000"AND CS='0'ELSE "01000001"WHEN ADDR="00001001"AND CS='0'ELSE "01010000"WHEN ADDR="00001010"AND CS='0'ELSE "00000100"WHEN ADDR="00001011"AND CS='0'ELSE "10011001"WHEN ADDR

27、="00001100"AND CS='0'ELSE "01010000"WHEN ADDR="00001101"AND CS='0'ELSE "00000100"WHEN ADDR="00001110"AND CS='0'ELSE "10100110"WHEN ADDR="00001111"AND CS='0'ELSE "10110000"WHEN ADDR="0

28、0010000"AND CS='0'ELSE "00000100"WHEN ADDR="00010001"AND CS='0'ELSE "11000010"WHEN ADDR="00010010"AND CS='0'ELSE "11011000"WHEN ADDR="00010011"AND CS='0'ELSE "00000000"END A;3.9 指令寄存器單元3.10 時(shí)序產(chǎn)

29、生器單元LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNTER ISPORT( Q,CLR: IN STD_LOGIC; T2,T3,T4: OUT STD_LOGIC );END COUNTER;ARCHITECTURE A OF COUNTER ISSIGNAL X: STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN PROCESS(Q,CLR) BEGIN IF(CLR='0'

30、) THEN T2<='0' T3<='0' T4<='0' X<="00" ELSIF(Q'EVENT AND Q='1') THENX<=X+1; T2<=(NOT X(1) AND X(0); T3<=X(1) AND (NOT X(0); T4<=X(1) AND X(0); END IF; END PROCESS; END A;3.11 操作控制器單元地址轉(zhuǎn)移邏輯電路ADDRLIBRARY IEEE;USE IEEE.STD_LOGIC_1164

31、.ALL;ENTITY ADDR IS PORT( I7,I6,I5,I4:IN STD_LOGIC; FS,T4,P1,P2:IN STD_LOGIC; SE6,SE5,SE4,SE3,SE2,SE1:OUT STD_LOGIC);END ADDR;ARCHITECTURE A OF ADDR ISBEGINSE6<='1'SE5<=NOT( FS AND P2 AND T4);SE4<=NOT(I7 AND P1 AND T4);SE3<=NOT(I6 AND P1 AND T4);SE2<=NOT(I5 AND P1 AND T4);SE1&

32、lt;=NOT(I4 AND P1 AND T4);END A;微地址寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY MMM IS PORT( SE:IN STD_LOGIC; T2:IN STD_LOGIC; D:IN STD_LOGIC; CLR:IN STD_LOGIC; UA:OUT STD_LOGIC );END MMM;ARCHITECTURE A OF MMM ISBEGIN PROCESS(CLR,SE,T2) BEGIN IF(CLR='0') THEN UA<='0' ELSIF(S

33、E='0')THEN UA<='1' ELSIF(T2'EVENT AND T2='1') THEN UA<=D; END IF; END PROCESS;END A;微地址轉(zhuǎn)換器F1LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F1 ISPORT(UA5,UA4,UA3,UA2,UA1,UA0:IN STD_LOGIC;D:OUT STD_LOGIC_VECTOR(5 DOWNTO 0);END F1;ARCHITECTURE A OF F1 ISBEGIND(5)<=

34、UA5;D(4)<=UA4;D(3)<=UA3;D(2)<=UA2;D(1)<=UA1;D(0)<=UA0;END A;控制存儲(chǔ)器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CONTROM ISPORT(ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); D:OUT STD_LOGIC_VECT

35、OR(18 DOWNTO 0) );END CONTROM;ARCHITECTURE A OF CONTROM ISSIGNAL DATAOUT: STD_LOGIC_VECTOR(24 DOWNTO 0);BEGIN PROCESS(ADDR) BEGINCASE ADDR ISEND CASE;UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0);D(18 DOWNTO 0)<=DATAOUT(24 DOWNTO 6);END PROCESS;END A;微命令寄存器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IE

36、EE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY MCOMMAND ISPORT( T2,T3,T4,I3,I2,I1,I0:IN STD_LOGIC; O:IN STD_LOGIC_VECTOR(18 DOWNTO 0); P1,P2,LOAD,LDPC,LDAR,LDIR,LDR0,LDR1,LDR2,R0_B,R1_B,R2_B,S1,S0,ALU_B,LDAC,LDDR,WR,CS,SW_B,LED_B,LDFR:OUT STD_LOGIC );END MCOMMAND;ARCHITECTURE A OF MCO

37、MMAND ISSIGNAL DATAOUT:STD_LOGIC_VECTOR(18 DOWNTO 0);BEGIN PROCESS(T2) BEGIN IF(T2'EVENT AND T2='1')THEN DATAOUT(18 DOWNTO 0)<=O(18 DOWNTO 0); END IF; P2<=DATAOUT(0); P1<=DATAOUT(1); LDFR<=DATAOUT(2) AND T4; LED_B<=DATAOUT(3); SW_B<=DATAOUT(4); CS<=DATAOUT(5); WR<

38、=DATAOUT(6)OR(NOT T3); LDDR<=DATAOUT(7) AND T4; LDAC<=DATAOUT(8) AND T4; ALU_B<=DATAOUT(9); S0<=DATAOUT(10); S1<=DATAOUT(11); R2_B<=(DATAOUT(13)OR(NOT I1)OR I0)AND(DATAOUT(12)OR(NOT I3)OR I2); R1_B<=(DATAOUT(13)OR(NOT I0)OR I1)AND(DATAOUT(12)OR(NOT I2)OR I3); R0_B<=(DATAOUT(1

39、3)OR I1 OR I0)AND(DATAOUT(12)OR I3 OR I2); LDR2<=T4 AND DATAOUT(14)AND I1 AND (NOT I0); LDR1<=T4 AND DATAOUT(14)AND (NOT I1) AND I0; LDR0<=T4 AND DATAOUT(14)AND (NOT I1) AND (NOT I0); LDIR<=DATAOUT(15)AND T3; LDAR<=DATAOUT(16)AND T3; LDPC<=DATAOUT(17)AND T4; LOAD<=DATAOUT(18); E

40、ND PROCESS;END A;微地址轉(zhuǎn)換器F2LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY F2 ISPORT(D:IN STD_LOGIC_VECTOR(5 DOWNTO 0);UA5,UA4,UA3,UA2,UA1,UA0:OUT STD_LOGIC);END F2;ARCHITECTURE A OF F2 ISBEGINUA5<=D(5);UA4<=D(4);UA3<=D(3);UA2<=D(2);UA1<=D(1);UA0<=D(0);END A;微地址轉(zhuǎn)換器F3LIBRARY IEEE;USE

41、IEEE.STD_LOGIC_1164.ALL;ENTITY F3 ISPORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0);UA7,UA6,UA5,UA4,UA3,UA2,UA1,UA0:OUT STD_LOGIC);END F3;ARCHITECTURE A OF F3 ISBEGINUA7<=D(7);UA6<=D(6);UA5<=D(5);UA4<=D(4);UA3<=D(3);UA2<=D(2);UA1<=D(1);UA0<=D(0);END A;3.12 頂層電路單元備注：SF，和LDRF輸出是個(gè)人用于仿真差錯(cuò)時(shí)候加入的，對于機(jī)器不影響。3.13 功能仿真與時(shí)序仿真如圖，輸入了五個(gè)數(shù)：82，01，02，03，F(xiàn)E，最后輸出結(jié)果02.結(jié)果正確。報(bào)告總結(jié)這個(gè)課設(shè)，我是從設(shè)計(jì)匯編程序開始的。和舍友針對程序要求，翻出匯編課本，寫出了第一版的程序