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1、Synopsys FPGA SynthesisSynplify Pro Quick Start GuideSeptember 2010Disclaimer of WarrantySynopsys, Inc. makes no representations or warranties, either expressed or implied, by or with respect to anything in this manual, and shall not be liable for any implied warranties of merchantability or fitness

2、 for a particular purpose of for any indirect, special or consequential damages.Copyright NoticeCopyright © 2010 Synopsys, Inc.s.Synopsys software products contain certaininformation ofSynopsys, Inc. Use of this copyright notice is precautionary and does not imply publication or disclosure. No

3、part of this publication may be repro- duced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form by any means without the prior written permission of Synopsys, Inc. While every precaution has been taken in the preparation of this book, Synopsys, Inc.

4、assumes no responsibility for errors or omissions. This publication and the features described herein are subjectto change without notice.TrademarksRegistered Trademarks (®)Synopsys, AMPS, Astro, Behavior Extracting Synthesis Technology, Cadabra, CATS, Certify, Design Compiler, DesignWare, Form

5、ality, HDL Analyst,HSPICE, Identify, iN-Phase, Leda, MAST, MTools, NanoSim, OpenVera,PathMill, Physical Compiler, PrimeTime, SiVL, SCOPE, Simply Better Results, SNUG, SolvNet, Synplicity, the Synplicity logo, Synplify, Synplify Pro, Synthesis Constraints Optimization Environment, TetraMAX, VCS, Vera

6、, and YIELDirector are registered trademarks of Synopsys, Inc.Trademarks ()AFGen, Apollo, Astro-Rail, Astro-Xtalk, Aurora, AvanWaves, BEST, Columbia, Columbia-CE, Cosmos, CosmosLE, CosmosScope, CRITIC, DCExpert, DC Professional, DC Ultra, Design Analyzer, Design Vision, Design- erHDL, DesignPower, D

7、irect Silicon Access, Discovery, Eclypse, Encore, EPIC, Galaxy, HANEX, HAPS, HapsTrak, HDL Compiler, Hercules, Hierar-Copyright © 2010 Synopsys, Inc. 2Synplify Pro Quick Start GuideSeptember 2010chical Optimization Technology, High-performance ASIC Prototyping System, HSIM, HSIMplus, i-Virtual

8、Stepper, IICE, in-Sync, iN-Tandem, Jupiter, Jupiter-DP, JupiterXT, JupiterXT-ASIC, Liberty, Libra-Passport, LibraryCompiler, Magellan, Mars, Mars-Rail, Mars-Xtalk, Milkyway, MSource,Module Compiler, MultiPoint, Physical Analyst, Planet, Planet-PL, Polaris, Power Compiler, Raphael, Saturn, Scirocco,

9、Scirocco-i, Star-RCXT,Star-SimXT, System Compiler, System Designer, Taurus, TotalRecall, TSUPREM-4, VCS Express, VCSi, VHDL Compiler, VirSim, and VMC are trademarks of Synopsys, Inc.Service Marks (SM)MAP-in, SVP Café, and TAP-in are service marks of Synopsys, Inc.SystemC is a trademark of the O

10、pen SystemC Initiative and is used under license. ARM and AMBA are registered trademarks of ARM Limited. Saber is a registered trademark of SabreMark Limited Partnership and is used under license. All other product or company names may be trademarks of their respective owners.Restricted Rights Legen

11、dGovernment Users: Use, reproduction, release, modification, or disclosure of this commercial computer software, or of any related documentation of any kind, is restricted in accordance with FAR 12.212 and DFARS 227.7202, and further restricted by the Synopsys Software License and Maintenance Agreem

12、ent. Synopsys, Inc., 700 East Middlefield Road, Mountain View, CA 94043, U. S. A.Printed in the U.S.A September 2010Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.3Copyright © 2010 Synopsys, Inc. 4Synplify Pro Quick Start GuideSeptember 2010ContentsChapter 1: Q

13、uick Start OverviewChapter 2: Process FlowProcess Flow Diagram13Top-Down and Compile Point Design Flows15Hierarchical Project Management Flows16Chapter 3: Set up Design InformationAdd Source Files19Select A Target Device20Set Implementation Options21State Machine Implementation21Resource Sharing22Pi

14、pelining22Retiming23Formal Verification24Chapter 4: Set up Timing InformationSet Timing Constraints28Define Compile Points29Set Constraints (Compile Point Synthesis)30Set Top-level Constraints30Set Compile Point Constraints30Run32Chapter 5: Analyze ResultsView the Log File35Use the HDL Analyst®

15、 Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.5PrefaceRTL View36Technology View37Design Hierarchy Exploration Tools37Advanced Find Capabilities40Filtered and Flattened View

16、s41Crossprobing Across Views45Cross-tool Crossprobing46Other Options47Mouse Strokes48Use FSM Viewer49Other Tools to Validate Synthesis Results52Use Formal Verification52Use syn_probe Attribute53Identify RTL Debugger53Chapter 6: Specify Directives and AttributesUsing Directives and Attributes55syn_ma

17、xfan56syn_keep57syn_ramstyle57Chapter 7: Basics of Timing ConstraintsSpecifying Timing Information60Clock Descriptions61Example61Clock Groups63Rise and Fall Constraints64Input and Output Delays66Input Ports67Output Ports69Multicycle Paths70Setting Multicycle Path Constraints71I/O Standard72Chapter 8

18、: Analyze Timing ResultsCritical Path Report73Timing Information Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Copyright © 2010 Synopsys, Inc. 6Synplify Pro Quick Start GuideSeptember 2010PrefaceCritical Path Analysis in a Technology View75Crit

19、ical Path Views76Generate a Technology View for the Most Critical Path76Generate Critical Path View in the Timing Analyzer77Generate Critical Path View from the Log File80Chapter 9: Refine Options to Improve TimingRefine Timing Results83Compare Synthesis Results with Place-and Route Results84Add Rou

20、te Delay Constraints85Forward Annotate Incremental Results86Chapter 10: Additional Features and TopicsSynplifyPhysical Synthesis90Synthesis Output Files91Output Netlist92Using Multiple Clock Domains93Using Scripts and Batch Mode93Using the Tcl Find Command for Setting Constraints93Running Place and

21、Route94Using Identify with Synplify Pro94For More Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.7PrefaceCopyright © 2010 Synopsys, Inc. 8Synplify Pro Q

22、uick Start GuideSeptember 2010CHAPTE R 1Quick Start OverviewWhat does the Synplify Pro software Offer? The Synplify Pro software consists of a fast, high-performance, sophisticated logic synthesis engine that utilizes proprietary technology called Behavior Extracting Synthesis Technology® (BEST

23、TM) tiver highly efficient FPGA and CPLD designs.Starting with Verilog and VHDL hardware description language input files, the software generates an optimized netlist in the most popular CPLD and FPGA vendor formats.Who Will Find This Guide Useful? This guide provides the steps and options of a desi

24、gn flow and can be used by:Engineers who want to evaluate the software without actually running it. The guide includes many graphic examples that show the capabilities of the software.Engineers who want to get a quick start to run synthesis.Managers who want to understand the capabilities and featur

25、es of the software before purchasing.How is the information organized? The document is organized as described below. You can click on the links in the columns to take you to the sections:Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.9Chapter 1: Quick Start Overview

26、Describes.PageProcess FlowThe top-down, Compile Point Synthesis, and Hierarchical Project Management flows.13Set up Design InformationThe steps used to set up your project for Synplify Pro synthesis.19Add Source Files19Select A Target Device20Set Implementation Options21Set up Timing InformationHow

27、to set general timing constraints and define compile points for the Compile Point Synthesis flow.2728Set Timing Constraints29Define Compile Points30Set Constraints (Compile Point Synthesis)How to synthesize the design.32RunAnalyze ResultsHow to view the synthesis results using the log file and some

28、built-in tools like the HDL Analyst tool for graphic analysis and the FSM viewer for state machine implementations. Also describes how to formally verify your results with LEC.33View the Log File35Use the HDL Analyst® Tool35Use FSM Viewer49Other Tools to Validate Synthesis Results52Use Formal V

29、erification52Use syn_probe Attribute53Identify RTL Debugger53Specify Directives and AttributesHow to use attributes and directives to fine-tune the way the design is synthesized.5556syn_maxfan57syn_keep57syn_ramstyleCopyright © 2010 Synopsys, Inc. 10Synplify Pro Quick Start GuideSeptember 2010C

30、hapter 1: Quick Start OverviewDescribes.PageBasics of Timing ConstraintsBasic timing concepts used in the Synplify Pro tool.5960Specifying Timing Information61Clock Descriptions63Clock Groups64Rise and Fall Constraints66Input and Output Delays70Multicycle Paths72I/O StandardAnalyze Timing ResultsHow

31、 to analyze timing results and use options to improve timing.73Critical Path Report73Timing Information Display75Critical Path Analysis in a Technology View75Refine Options to Improve Timing8383Refine Timing Results84Compare Synthesis Results with Place- and Route ResultsForward Annotate Incremental

32、 ResultsHow to forward annotate incremental results (updates) in a Compile Point Synthesis flow so that your complete design project is up- to-date.86Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.11Chapter 1: Quick Start OverviewDescribes.PageAdditional Features an

33、d Topics:Additional features and options for synthesis.89SynplifyPhysical Synthesis90Synthesis Output Files91Using Multiple Clock Domains93Using Scripts and Batch Mode93Using the Tcl Find Command for Setting Constraints93Running Place and Route94Using Identify with Synplify Pro94Copyright © 201

34、0 Synopsys, Inc. 12Synplify Pro Quick Start GuideSeptember 2010CHAPTE R 2Process FlowThe Synplify Pro software is designed to give you the best overall circuit performance with a minimal amount of effort.Topics include the following process flows:Process Flow Diagram, on page 13Top-Down and Compile

35、Point Design Flows, on page 15 Hierarchical Project Management Flows, on page 16Process Flow DiagramThe following figure shows you two Synplify Pro flows with simple steps to trade off between timing and area to help you reach your goals quickly.The top-down flow is the traditional synthesis flow wi

36、th a global approach to synthesis. With the Compile Point Synthesis flow, you can design incremen- tally and synthesize only what is necessary.Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.13Chapter 2: Process FlowProcess Flow DiagramTop-Down FlowCompile Point Synt

37、hesis FlowAdd Source FilesAdd Source FilesSet up design informationSet up design informationSelect A Target Device Set Implementation OptionsSelect A Target Device Set Implementation OptionsSet up timing informationSet Timing ConstraintsView the Log FileAnalyze implementation resultsAnalyzeUse the H

38、DL Analyst® ToolUse FSM Viewer Other Tools to Validate Synthesis ResultsView the Log FileUse the HDL Analyst® Tool Use FSM ViewerOther Tools to Validate Synthesis ResultsTiming ResultsAnalyze Timing ResultsYesMeets requirements?NoYesMeets requirements?NoRefine Options to Improve TimingSpec

39、ify Directives and AttributesRefine Options to Improve TimingCopyright © 2010 Synopsys, Inc. 14Synplify Pro Quick Start GuideSeptember 2010Specify Directives and AttributesRunForward AnnotateIncremental ResultsRunAnalyze implementation resultsDefine Compile PointsSet Constraints (Compile Point

40、Synthesis)Top-Down and Compile Point Design FlowsChapter 2: Process FlowTop-Down and Compile Point Design FlowsA Compile Point Synthesis flow differs from a traditional top-down flow in that it divides the design into parts that can be processed independently or synthesized incrementally, using a te

41、am design approach. Unlike other bottom-up solutions, it is highly automated and eliminates the need for time consuming and error prone scripts. Compile point synthesis is based on compile points, which are smaller synthesis units of the main design that are treated as individual blocks.The Compile

42、Point Synthesis flow is available for certain design families. Check the Device tab of the Implementation Options dialog box for applicable technology families. For Altera designs, you can use this flow with the AlteraQuartus II Incremental Compilation methodology to pesign imple-mentation data so a

43、s to make incremental place and route updates.Similarly, you can use the Xilinx Incremental flows with the place-and-route tool for team-based design. See the Synplify Pro software documentation and the appropriate application notes for details.Synplify Pro Quick Start Guide September 2010Copyright

44、© 2010 Synopsys, Inc.15Chapter 2: Process FlowHierarchical Project Management FlowsHierarchical Project Management FlowsAs designs grow in size and complexity, the industry uses team design and parallel development techniques to ensure that designs are finished on time. Typically, designs are s

45、plit into smaller sub-projects or blocks, and different teams work on different blocks. The team design approach could be either top-first or block-first. The hierarchical project management capabilities in the FPGA synthesis tools facilitate both the top-first or block-first team design approaches.

46、Top-FirstIn this flow, you start with the top-level design and then divide it up into sub-projects (blocks). The block RTL is included in the top-level project. The advantage to using this approach is that you can take advantage of boundary optimizations to improve QOR.Block-FirstIn this design appr

47、oach, blocks (sub-projects) are developed indepen- dently and then stitched together at the top level. The advantage to this approach is independence, parallel development, and fewer design constraints at the team level. In the following example, different teams work on each block and the blocks are

48、 then integrated into the top level.Block-First Development FlowTop-First Development FlowTopHierarchical project management consists of various features and methodolo- gies that help you develop and automatically manage a single FPGA project using multiple teams across different geographical areas.

49、 These flows are intended for distributed design development, and for parallel development of portions of the design. You create partitions at the RTL level, but you do not have to floorplan them. The hierarchical project management flows are modular, and can use compile points for its block-level c

50、omponents.Copyright © 2010 Synopsys, Inc. 16Synplify Pro Quick Start GuideSeptember 2010B2B1TopB2B1Hierarchical Project Management FlowsChapter 2: Process FlowHierarchical project management includes features like a GUI that supports hierarchical project management and module import and export,

51、 top-first, block-first and mixed development flows, and both top-down and bottom-up synthesis flows. Hierarchical Project Management process flows include:Block-First Development Flow for Hierarchical Projects Top-First Development Flow for Hierarchical Projects Creating Sub-Projects in Top-First D

52、esignsWorking with Multiple Implementations in Hierarchical Projects Top-Down Synthesis for Hierarchical ProjectsBottom-Up Synthesis for Hierarchical Projects Mixed Block Synthesis for Hierarchical ProjectsAnalyzing Synthesis Results for Hierarchical ProjectsFor more information, see Hierarchical Pr

53、oject Management Flows in the User Guide.Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.17Chapter 2: Process FlowHierarchical Project Management FlowsCopyright © 2010 Synopsys, Inc. 18Synplify Pro Quick Start GuideSeptember 2010CHAPTE R 3Set up Design Informati

54、onThere are three basiks involved in setting up a design. Both the top-down and Compile Point Synthesis flows use the same design setup. Topics include:Add Source Files, on page 19 Select A Target Device, on page 20Set Implementation Options, on page 21Add Source FilesAfter you have installed the so

55、ftware, set up the design project. Then, add source files.Project fileSource files, with top-level file lastSource files need to be ordered such that the top-level file is last in the source file list. If you have mixed language source files (a combination of Verilog and VHDL files), specify the top-level file using Implementation Options ->Verilog or VHDL tab, as shown below.Synplify Pro Quick Start Guide September 2010Copyright © 2010 Synopsys, Inc.19Chapter 3: Set up Design InformationSelect A Target DeviceSelect A Target DeviceChoose the technology family using the