簡(jiǎn)易類型識(shí)別器練習(xí)

1、明德?lián)P科技教育簡(jiǎn)易類型識(shí)別器練習(xí)網(wǎng)：官淘寶：群目錄pkt_check 模塊3pkt_check_tb 模塊10明德?lián)P科技公司主要是以 FPGA 為，專業(yè)從事 FPGA 配套開(kāi)發(fā)板、FPGA 培訓(xùn)班或其他培訓(xùn)、研發(fā) FPGA 技術(shù)開(kāi)發(fā)、承接 FPGA 項(xiàng)目開(kāi)發(fā)。歡迎加入明德?lián)P FPGA 和 ASIC97925396。明德?lián)P以 PDF 格式提供源代碼，是為了鼓勵(lì)大家多思考，不要拿來(lái)就用，否則是學(xué)不好 FPGA 的。本代碼對(duì)應(yīng)的設(shè)計(jì)思路，請(qǐng)參考明德?lián)P課程。pkt_check 模塊module pkt_check(clk rst_ndin,dout_vld,dout,dout_sop,dout_eop

2、);/參數(shù)定義parameterDATA_W = 8;parameter parameter parameter parameter parameter parameter/輸入信號(hào)定義input inputHEAD TYPE LEN DATAFCS= 0;= 1;= 2;= 3;= 4;CTRL_PKT_LEN=64;clk rst_ndin;input DATA_W-1:0/輸出信號(hào)定義 outputDATA_W-1:0 outputoutputoutputdout dout_sop; dout_eop;dout_vld;/輸出信號(hào) reg 定義reg reg regregDATA_W-1

3、:0dout dout_sop; dout_eop;dout_vld;reg 2:0reg 2:0reg 3:0 reg reg15:0 regreg1:0sse_c;e_n;t; head_flag;t;t;t;always(edge clk or negedge rst_n)beginif(rst_n=1b0)beginse_c = HEAD;endelse beginse_c = se_n;endendalways(*)begin case(se_c)HEAD:beginif(t=9 & din=8hd5)beginse_n = TYPE;endelse beginse_n = HEAD

4、;endend TYPE:beginif(din=0)beginse_n = DATA ;endelse beginse_n = LEN;endend:beginif(LENt=1)beginse_n = DATA;endelse beginse_n = LEN;endend:beginif(DATAt=0)begine_n = FCS;sendelse beginse_n = DATA;endend:beginif(FCSt=3)begine_n = HEAD;sendelse beginse_n = FCS;endendendcaseendalways(edge clk or negedg

5、e rst_n)beginif(rst_n=1b0)begint = 0;endelse if(se_c=HEAD) begin if(head_flag=0) beginif(din=8h55)begint =endelse begint = 0;endendt + 1;else if(head_flag=1)beginif(din=8hd5)beginif(t=9)begint = 0;endelse begint =t + 1;endendelse if(din=8h55) begint = 1;endelse begint = 0;endendendelse begint = 0;en

6、dendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin head_flag = 1b0;endelse if(se_c=HEAD) begin if(head_flag=1b0)beginif(din=8h55)head_flag = 1b1;endelse beginif(din=8h55)begin head_flag = 1b1;endelse beginhead_flag = 1b0;endendendelse beginhead_flag = 1b0;endendalways(edge clk or negedge r

7、st_n)beginif(rst_n=1b0)begint = 0;endelse if(se_c=TYPE & din=0) begint = CTRL_PKT_LEN-1;end else if(sif(e_c=LEN)begin t=0)begint = t7:0,din;endelse begint = t7:0,din-1;endendelse if(t!=0)begint =t - 1;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begint = 1b0;endelse if(se_c=LEN) begint =

8、 t;endelse begint = 1b0;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begint = 0;endelse if(se_c=FCS)beginif(t=3)t = 0;elset =t + 1;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin dout = 0;endelse begindout = din;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begi

9、n dout_vld = 1b0;endelse if(se_c != HEAD) begin dout_vld = 1b1;endelse begindout_vld = 1b0;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin dout_sop = 1b0;endelse if(se_c=TYPE) begin dout_sop = 1b1;endelse begindout_sop = 1b0;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)beg

10、in dout_eop = 1b0;endelse if(se_c=FCS & dout_eop = 1b1;endelse begint=3) begindout_eop = 1b0;endendendmodulepkt_check_tb 模塊timescale1ns/1nsmodulepkt_check_tb;parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameter parameterparameterSE_WID=6;8;3;7

11、;2;16;3;6b0000_01;6b0000_10;6b0001_00;6b0010_00;6b0100_00;6b1000_00;DATA_WID WAIT_WID LOAD1_WID LEN_WID LOAD2_WID FCS_WID WAIT PKT_TYPE PLAYLOAD1 LENGTH PLAYLOAD2FCSreg reg reg wire wire wirewireclk; rst_n; din; vld_out; dout; sop;eop;DATA_WID-1:0DATA_WID-1:0wire wire wirewirevld_out1; dout1; sop1;e

12、op1;DATA_WID-1:0regcom_flag ;pkt_checkuut_message_check1(.clk.rst_n.din.dout_vld.dout.dout_sop.dout_eop(clk),(rst_n),(din), (vld_out1), (dout1),(sop1),(eop1);initial begin #10clk=1; forever #5clk=clk;endinitial begin rst_n=1; #5rst_n=0; #5rst_n=1;endinitial begin #2din=1;/開(kāi)頭發(fā)送 1 個(gè) 0 x55，再發(fā)送 5 個(gè) 0 x5

13、5d5，pkt_type=0 #10din=8h55; repeat(5) begin#10din=8h55; #10din=8hd5; end#10din=0; repeat(68) begin#10din=din+1; end/間隔 3 個(gè)時(shí)鐘周期repeat(3) begin #10din=10;end/出現(xiàn) h55d5，h5555，5 個(gè)h55d5 情況pkt_type=0#10din=8h55; #10din=8hd5; #10din=8h55; #10repeat(5) begin#10din=8h55; #10din=8hd5; end#10din=0; repeat(68) b

14、egin#10din=din+1; end/緊接著上一個(gè)報(bào)文，pkt_type=0repeat(5) begin#10din=8h55; #10din=8hd5; end#10din=0; repeat(64) begin#10din=din+1; endrepeat(2) begin#10din=8h55; #10/din=8hd5; end#10din=0; repeat(10) begin#10din=din+1; end/無(wú)效數(shù)據(jù)/開(kāi)頭發(fā)送 2 個(gè) 0 x55d5,1 個(gè) 0 x55,再發(fā)送 5 個(gè) 0 x55d5,pkt_type=1,length=10 repeat(2)begin

15、#10din=8h55; #10din=8hd5; end#10din=8h55; repeat(5) begin#10din=8h55; #10din=8hd5; end#10din=1; #10din=0; #10din=10; repeat(10) begin#10din=din+1; end/開(kāi)頭發(fā)送 2 個(gè) 0 x55d5,再發(fā)送無(wú)關(guān)數(shù)據(jù),然后發(fā)送 5 個(gè) 0 x55d5,pkt_type=1,length=1 repeat(2)begin#10din=8h55;#10din=8hd5; end repeat(3) begindin=4; end repeat(5) begin#10

16、din=8h55; #10din=8hd5; end#10din=1; #10din=0; #10din=1; repeat(5) begin#10din=din+1; end#100;repeat(5) begin#10din=8h55; #10din=8hd5; end#10din=1; #10din=8h01; #10din=8h2c; repeat(304) begin#10din=din+1;endendalways(edge clk or negedge rst_n)beginif(rst_n=1b0)begin com_flag = 0;endelse beginif(vld_out=vld_out1)begin com_flag = 0;endelse begincom_flag = 1; end if(dout=dout1)begincom_fla