“射頻電路設(shè)計的關(guān)鍵技術(shù)和技巧”專題講座講義3

1、 Lecture 2 : Voltage and Power Transportation Richard Chi-Hsi Li 李緝熙 Email : 1. Voltage Delivered from a Source to a Load o General Expression of Voltage Delivered from a Source to a Load o Additional jitter or Distortion in a Digital Circuit Block 2. Power Delivered from a Source to a Load o Genera

2、l Expression of Power Delivered from a Source to a Load o Power Instability o Additional Power Loss o Additional Distortion o Additional interference3. Impedance Conjugate Matching o Maximization of Power Transportation o Power Transportation without Phase Shift o Impedance Matching Network o Necess

3、ity of Impedance Matching 4. Additional Effect of Impedance Matching o Voltage Pumped up by Impedance Matching o Power MeasurementLecture 211. Voltage delivered from a source to a loado General expression of voltage delivered from source to load Figure 1 Voltage delivered from a source to a loadSLZo

4、RSXS ZSSourcePSvS XL ZLLoadRLLecture 22tl (Delay time =Td) SourceLoadFigure 2 Voltages bouncing back and forth arrive at load when t =Td . Note: kv = RL/(ZS+ZL)Voltage delivered from Source:Voltage delivered from Source:-12Td -11Td Voltage delivered from Source:Voltage delivered from Source:-10Td -9

5、Td -8Td 2Td 1Td -1Td 0 -3Td -2Td -5Td -4Td -7Td -6Td Voltage delivered from Source:Voltage delivered from source: Voltage delivered from Source:Voltage arrived at RL ,Lecture 23Lecture 24 , o Additional Jitter or Distortion in a Digital Circuit BlockLecture 25Table 1 Additional distortion and additi

6、onal jitter in voltage transportation when f = 3.86 GHz S, %L, % D,% f, GHz T, ns Jitter, % Jitter, ps00 3.86 0.2590.00 050 3.860.2590.00 0100 3.860.2590.00 0200 3.860.2590.00 0500 3.860.2590.00 0053.860.2590.00 0553.860.2591053.860.259 2053.860.2595053.860.2590103.860.2590.00 05103.860.259 10103.86

7、0.25920103.860.25950103.860.259 0203.860.259 0.00 05203.860.25910203.860.25920203.860.25950203.860.2590503.860.2590.00 05503.860.25910503.860.25920503.860.25950503.860.259Lecture 26 , and then,1) when , and then,2) when , and then,3) when The voltage reflection becomes pernicious. The voltage reflec

8、tion seems not too harmful. The voltage reflection is horrible!Lecture 272. Power delivered from a source to a loado General expression of power delivered from source to loadFigure 2 Power delivered from a source to a loadSLZoRSXS ZSSourcePSvS XL ZLLoadRLLecture 28tl (Delay time =Td) SourceLoadFigur

9、e 4 Powers bounce forth and back and arrive at load when t =Td . (Note: kp=RL/|ZS+ZL|2)Power delivered from source:Power delivered from source:-12Td -11Td Power delivered from source:Power delivered from source:-10Td -9Td -8Td 2Td 1Td -1Td 0 -3Td -2Td -5Td -4Td -7Td -6Td Power delivered from source:

10、Power delivered from source:Power delivered from source:Power arrived at RL ,Lecture 29o Power InstabilityLecture 210o Additional Power LossLecture 211 Table 2 Additional power loss due to the unmatched case when = -30 dBm.S, %L, % ,dBm ,dBm ,dBm000.0000 -30-infinite-30500.0000 -30 -infinite-301000.

11、0000-30 -infinite-302000.0000-30-infinite-305000.0000-30 -infinite-30050.0500-30 -43.01-30.22550.0476 -30 -43.22-30.211050.0452-30-43.45-30.202050.0404-30-43.94-30.185050.0256 -30-45.91-30.110100.1000 -30 -40.00-30.465100.0955 -30 -40.20-30.4410100.0909-30-40.41-30.4120100.0816 -30 -40.88-30.3750100

12、.0526-30-49.79-30.230200.2000-30-36.99-30.975200.1919-30-37.17-30.9310200.1837 -30-37.36-30.8820200.1667 -30-37.78-30.7950200.1111-30-354-30.510500.5000-30-33.01-33.015500.4872-30-33.12-39.9010500.4737-30-33.25-39.7920500.4444-30-33.52-39.5550500.3333-30-34.77-31.76Lecture 212o Additional Distortion

13、Lecture 213Table 3 Additional distortion in power transportation S, % L, % Dp,% 000.00 500.00 1000.00 2000.00 5000.00 0529.365521.8210521.2720520.1050516.0101031.6251030.90101030.15201028.57501029.9402044.7252043.81102049.86202040.82502033.3305070.7155068.00105068.82205066.67505057.74 Lecture 214Fro

14、m Table 3 it can be seen that In cases where L = 0, there is no additional distortion. On the contrary, in the cases of L 0, the additional distortion is appreciable! The additional distortion is more sensitive to the value of L than to the value of S, For given value of L, the additional distortion

15、 is somewhat reduced as the value of S is increased. For given value of S, the additional distortion is somewhat increased as the value of L is increased. The highest value of the additional distortion in Table 9.3 is 70.71% when S=0 and L =50%.Lecture 215o Additional InterferenceLecture 216 Table 4

16、 Calculated ratio of signal to interference as the reflection coefficient, , is varied.S, L,% % dB W % W W dB0015 31.620.00000.00001.0015.005015 31.62 0.00000.00001.0015.0010015 31.620.00000.00001.0015.0020015 31.620.00000.00001.0015.0050015 31.62 0.00000.00001.0015.000515 31.620.00000.00001.0015.00

17、5515 31.620.00250.00251.0814.6710515 31.620.00500.00501.1614.3620515 31.620.01000.01011.3213.8050515 31.620.02500.02561.8112.4201015 31.620.00000.00001.0015.0051015 31.620.00500.00501.1614.36101015 31.620.01000.01011.3213.80201015 31.620.02000.02041.6512.84501015 31.620.05000.05262.6610.7402015 31.6

18、20.00000.00001.0015.0052015 31.620.01000.01011.3213.80102015 31.620.02000.02041.6512.84202015 31.620.04000.04172.3211.35502015 31.620.10000.11114.51 8.4505015 31.620.00000.00001.0015.0055015 31.620.02500.02561.8112.42105015 31.620.05000.05262.6610.74205015 31.620.10000.11114.51 8.45505015 31.620.250

19、00.333311.54 4.38Lecture 217From Table 4 it can be seen that In cases where L = 0, there is no additional interference, so the SIR is kept unchanged. The additional interference is more sensitive to the value of L than to the value of S, For a given value of L, the additional interference increases

20、as the value of S increases so that the SIR is reduced. For a given value of S, the additional interference increases as the value of L increases so that the SIR is reduced. The highest value of the additional interference in Table 9.4 is reached when S=50% and L=50%. At this point the SIR drops fro

21、m 15 dB to 4.38 dB.Lecture 218 o Maximizing of Power Transportation , or, , or , or, 3. Impedance Conjugate MatchingFigure 5 Power delivered from a source to a load without reflectionS= 0L= 0ZoRSXS ZSSourcePSvS XL ZLLoadRLLecture 219This is called “neutralization of reactance between source and load

22、. o Power Transportation without Phase Shift Figure 6 Two matching cases when reactance of source is “neutralized” by reactance of load, or, vice versa, that is, XS = -XL(a) RS in series with XS (b) RS in parallel with XS RL in series with XL RL in parallel with XLRSRLvS vLXSXL“Neutralization”of rea

23、ctanceRSRLvL XLXS“Neutralization”of reactancevS Lecture 220(c) 8PSK(b) 4PSK(a) BPSK(e) 16QAM(f) 64QAM9.46oFigure 7 Progress of modulation technology from PSK to QAM(d) 16PSK22.5o26.56oLecture 221Lecture 222 A matching network must be inserted between source and load so that the impedance matching co

24、ndition can be satisfied as following :o Impedance Matching NetworkUsuallyRSvSXSSourcePSXLRLLoadFigure 8 An impedance matching network is inserted between source and load when ZS ZL* Impedance MatchingNetworkZinZoutZSZLPinPoutLecture 223XLRLOld LoadRSvSXSOld SourcePSFigure 9 First sub- impedance mat

25、ching loop: *New source = old source, *New load = Impedance matching network + old load Impedance Matching NetworkZinZoutZSZLPinPoutNew Source=Old sourceXinRinNew load=Impedance matching network +old loadvinLecture 224Figure 10 Second sub- impedance matching loop: the impedance matching network itse

26、lf Impedance MatchingNetworkZinZoutPinPoutRinXinRoutXoutLecture 225RSvSXSOld SourcePSXLRLOld LoadFigure 11 Third sub-impedance matching loop: *New source = Old source+ Impedance matching network *New load = Old load Impedance Matching NetworkZinZoutZSZLPinPoutNew load=Old loadXoutRoutNew source= old

27、 source + Impedance matching network Lecture 226RSvSXSSourcePSXLRLLoadFigure 8 An impedance matching network is inserted between source and load when ZS ZL* Impedance MatchingNetworkZinZoutZSZLPinPoutLecture 227o Necessity of Impedance MatchingIs this impedance matching network necessary ?Figure 12

28、A source follower (DC bias is neglected)VddInRoOutVddInRoImpedanceMatching Network OutZx(a) Primary source follower(b) “Improved” source follower?Is it necessary to insert an impedance matching network between two parts (Inductor, capacitor, resistor) ?Lecture 228(a) A primary MOSFET cascode amplifi

29、erCZeroBias 1Bias 2VddOutRF chokeRF chokeInRdM1M2Figure 13 A MOSFET cascode amplifier(b) An impedance matching network inserted between two stagesCZeroBias 1Bias 2VddOutRF chokeRF chokeInRdM1M2ImpedanceMatching NetworkIs this impedance matching network necessary ?Lecture 2294. Additional effects of

30、impedance matchingZLO = 3.35 j105.5 in seriesZLO = 3.325k / 0.39pF in parallelFigure 14 Conversion of impedance at LO port of a mixer (f = 3.86 GHz)LOZLOLOZLODevice0.39 pF3.325 LOZLODevice3.325 ZLO 3.325k, if 0.39 pF is neutralized. (Measured) Is it necessary to match LO portion ? Some engineers des

31、ign mixer without matching of LO portion. The reasons are Instead of power, only voltage is needed to ON/OFF the devices.As long as the runner from LO source to LO injection gate is short enough, the voltage from source would be directly effective on the gate.Or, one can simply put a 50 on LO inject

32、ion gate for matching to 50 source.o Voltage Pumped Up by Impedance MatchingLecture 230Rs=50 vgDevicevsVRs=50 DevicevgRs=50 Rg=50 vgDevicevsVvsVMatchingNetworkRs=50 vgDeviceRL=3.325 kRs=50 RL=3.325 kDevicevgvs=VRs=50 Rg=50 vgDeviceRL=3.325 kvs=VvsV(a) At LO port, the impedance matching is ignored.(b

33、) At LO port, a 50 resistor is connected in parallelAt LO port, impedance is well-matched by inserting of a matching network between the LO injection source and the LO injection port.)MatchingNetworkPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPs=0 dBmPg= -3 dBmLO portEquivalent circuitFigure 15 Three di

34、fferent ways for impedance matching at the LO port of a mixerLecture 231by power meter or spectrum analyzero Additional effects of impedance matching* Power MeasurementFigure 16 Output power of a tested block is measured by a power meter or a spectrum analyzer.PPEquivalentTested circuitvSZS*50 ZSPow

35、er meterOrSpectrum AnalyzerMatchNetwork(ZS* to 50 ohms)(a) Matched caseEquivalentTested circuitvSPL50 ZSPower meterOrSpectrum Analyzer(b) Un-matched case PL50 Lecture 232* Power Measurement by spectrum analyzer (Matched case)(a) Matched caseTested BlockvSZS*vL, PL50 ZSSpectrumAnalyzerMatchNetwork(ZS

36、* to 50 )Figure 17 Power measurement by spectrum analyzerLecture 233* Power Measurement by spectrum analyzer (Un-matched case)RS,XS PL/PoPL/Po, (ohms)(ohms) (dB) (b) Un-matched case Tested BlockvSvL, PL50 ohmsZSspectrum AnalyzerFigure 18 Power measurement by spectrum analyzerTable 5 Calculated value

37、s of PL/Po in un-matched case (b)Lecture 234 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9 10 100 1000 10000XS , P*/P, dB0-10-20-30-40-50RS =10 RS =50 RS =100 RS =1000 RS =10000 Figure 20 Plot of calculated power ratio, PL*/Po , vs. impedance of DTU, ZS.Impedance of power meter or others = 50 Lect

38、ure 235o Burning of the deviceHigh Power PARSVSiRLLZoutZinFigure 19 Possible burning of devices in the bench work for a PA.Lecture 236Voltage Standing Wave Ratio in dB: Appendix A VSWR and Other Reflection and Transmission CoefficientsPower reflection coefficient:Transmitted power in %:Reflected pow

39、er in %:Transmission loss in dB:Return loss in dB:Voltage reflection coefficient:Voltage Standing Wave Ratio:Note : r= R/Ro, Ro = 50 ohmLecture 237Table A.1 Relationships between impedance, reflection coefficient, transmission coefficient, and other parameters along with the axis U(V=0) in the compl

40、ex plane of voltage reflection coefficient R,(Ro = 50)r=R/Ro|VSWRVSWRdB (S11 or S22)RLdBTLdB PT,%PR,% 14.00660.28010.563.5711.06-5.000-1.65090.3268.3631.64 Lecture 238關(guān)于舉辦“射頻電路設(shè)計的關(guān)鍵技術(shù)和技巧專題講座的邀請函各有關(guān)單位： 為了促進(jìn)我國射頻電路應(yīng)用設(shè)計產(chǎn)業(yè)的開展，提高射頻電路設(shè)計水平和能力，學(xué)習(xí)和借鑒國外的先進(jìn)技術(shù)和經(jīng)驗(yàn)，中國電子電器可靠性工程協(xié)會決定組織召開第六期“射頻電路設(shè)計的關(guān)鍵技術(shù)和技巧專題講座。講座將聘實(shí)戰(zhàn)經(jīng)

41、驗(yàn)豐富的資深美籍華人專家講解射頻電路應(yīng)用設(shè)計技術(shù)和經(jīng)驗(yàn)。具體事宜通知如下：一、課程特色討論和強(qiáng)調(diào)射頻電路設(shè)計的根本技術(shù)和技巧; 譬如,阻抗匹配,射頻接地, 單端線路和差分線路之間的主要差別, 射頻集成電路設(shè)計中的難題可以把它歸類為橫向論述. 到目前為止，這種著重于設(shè)計技巧的論述是前所未有的，也是很獨(dú)特的。講演者認(rèn)為，作為一位合格的射頻電路設(shè)計的設(shè)計者，不管是工程師，還是教授，應(yīng)當(dāng)掌握這一局部所論述的根本的設(shè)計技術(shù)和技巧, 包括：阻抗匹配；接地；射頻集成電路設(shè)計；6 Sigma 設(shè)計。二、學(xué)習(xí)目標(biāo)：在本講座結(jié)束之后， 學(xué)員可以了解到：o比照數(shù)碼電路，射頻電路設(shè)計的主要差別是什麼? o什么是射頻設(shè)

42、計中的根本概念?o在射頻電路設(shè)計中如何做好窄帶的阻抗匹配？o在射頻電路設(shè)計中如何做好寬帶的阻抗匹配？o在射頻線路板上如何做好射頻接地的工作?o為什么在射頻和射頻集成電路設(shè)計中有從單端至雙差分的趨勢?o為什么在射頻電路設(shè)計中容許誤差分析如此重要?o什么是射頻和射頻集成電路設(shè)計中的主要難題？射頻和射頻集成電路設(shè)計師如何克服這些障礙?Lecture 239三、課程提綱：講課內(nèi)容屆時根據(jù)實(shí)際情況會有所調(diào)整。 第一講 射頻和數(shù)字電路的不同設(shè)計方法1.爭論阻抗匹配關(guān)鍵參數(shù)線路測試和主要測試設(shè)備 在通訊系統(tǒng)中射頻和數(shù)字方塊的差異阻抗電流 方塊位置結(jié)論給高速數(shù)字電路設(shè)計提點(diǎn)意見 第二講 電壓和功率傳輸1從源發(fā)

43、送電壓至負(fù)載2從源發(fā)送電壓至負(fù)載的一般表達(dá)式在數(shù)字電路方塊中的附加Jitter 或畸變。從源發(fā)送電壓至負(fù)載的一般表達(dá)式功率的不穩(wěn)定性 附加的功率損失附加畸變附加干擾阻抗共軛匹配2.3.最大的功率傳輸無相移的功率傳輸阻抗匹配網(wǎng)絡(luò) 阻抗匹配的必要性 阻抗匹配的附加效應(yīng)借助于阻抗匹配來抬高電壓功率測量；附錄：2A.1電壓駐波比VSWR 和其他反射及傳輸系數(shù)；2A.2功率 (dBm), 電壓 (V), 和功率(Watt)之間的關(guān)系；第三講 在窄帶情況下的阻抗匹配引言借助于返回?fù)p失的調(diào)整進(jìn)行阻抗匹配在Smith圖上的返回?fù)p失圓返回?fù)p失和阻抗匹配的關(guān)系阻抗匹配網(wǎng)絡(luò)的建造 一個零件的阻抗匹配網(wǎng)絡(luò)在阻抗匹配網(wǎng)

44、絡(luò)串接一個零件 在阻抗匹配網(wǎng)絡(luò)并接一個零件兩個零件的阻抗匹配網(wǎng)絡(luò)在Smith圖上的區(qū)域劃分零件的數(shù)值線路的選擇三個零件的阻抗匹配網(wǎng)絡(luò)3.5.1“ and “T 型的匹配網(wǎng)絡(luò)推薦的匹配網(wǎng)絡(luò)線路當(dāng) ZS 或 ZL 不是50 的阻抗匹配阻抗匹配網(wǎng)絡(luò)的零件附錄：1Smith 圖的根底知識 2兩個零件阻抗匹配網(wǎng)絡(luò)的公式3兩個零件阻抗匹配網(wǎng)絡(luò)的線路限制4三個零件阻抗匹配網(wǎng)絡(luò)的線路限制5在 “ 和“T 型的匹配網(wǎng)絡(luò)之間的轉(zhuǎn)換6可能的 “ 和 “T 型的匹配網(wǎng)絡(luò)第四講 在寬帶情況下的阻抗匹配 寬窄帶返回?fù)p失在Smith圖上的表現(xiàn)。接上每臂或每分支含有一個零件之后阻抗的變化在阻抗匹配網(wǎng)絡(luò)串接一個電容在阻抗匹配網(wǎng)

45、絡(luò)串接一個電感在阻抗匹配網(wǎng)絡(luò)并接一個電容在阻抗匹配網(wǎng)絡(luò)串接一個電感接上每臂或每分支含有兩個零件之后阻抗的變化兩個零件串接在一起形成一臂 4.3.2兩個零件并接在一起形成一分支超寬帶系統(tǒng)IQ 調(diào)制器 設(shè)計的阻抗匹配在IQ 調(diào)制器中的Gilbert Cell 。4.4.2Gilbert Cell的阻抗不考量帶寬在LO, RF and IF 終端的阻抗匹配超寬帶系統(tǒng)對帶寬的要求。4.4.5擴(kuò)展帶寬的根本思路。第一個例子: 在超寬帶系統(tǒng)第一組IQ 調(diào)制器設(shè)計中的阻抗匹配第二個例子: 在超寬帶系統(tǒng)第三和第六組IQ 調(diào)制器設(shè)計中的阻抗匹配4.5Discussion of Wide-band Impedance Matching Network4.5.1MOSFET 管子?xùn)艠O的阻抗匹配4.5.2MOSFET 管子漏極的阻抗匹配第六講阻抗測量 ：引言標(biāo)量和矢量的電壓測量 示波器的電壓測量矢量電壓計的電壓測量用網(wǎng)絡(luò)分析儀直接測量阻抗 阻抗測量的方向性6.3.2S 參數(shù)測量的好處6.3.3S 參數(shù)阻抗測量的理論背景用矢量電壓計測量S 參數(shù)網(wǎng)絡(luò)分析儀的校準(zhǔn)借助于網(wǎng)絡(luò)分析儀的另一種阻抗測量6.4.1Smith 圖的精度上下阻抗的測量借助于循環(huán)器的阻抗測量附錄：阻抗串并聯(lián)接之間的關(guān)系第七講：接地：接地的涵義在線路圖中可能隱