數(shù)字邏輯：5.5.3 VHDL語言的描述風(fēng)格

5.5.3VHDL語言的描述風(fēng)格三種描述風(fēng)格：

行為描述：使用功能描述

數(shù)據(jù)流（寄存器傳輸）：使用布爾代數(shù)式描述

結(jié)構(gòu)描述：模塊間的連接關(guān)系描述

5.5.4基本邏輯電路的VHDL設(shè)計一、組合電路原則1：在process中用到的所有輸入信號都出現(xiàn)在敏感信號列表中；原則2：電路的真值表必須在代碼中完整的反映出來。(否則會生成鎖存器)1.三態(tài)門及總線緩沖器－－指定大寫“Z”表示高阻態(tài)

a<=‘Z’;a_bus<=“ZZZZZZZZ”;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.all;ENTITYtri_gateISport(din,en:INstd_logic;dout:OUTstd_logic);ENDtri_gate;

ARCHITECTUREartOFtri_gateISBEGIN

PROCESS(din,en)

BEGIN

IF(en=‘0’)thendout<=din；

ELSEdout<=‘Z’;

ENDIF；

ENDPROCESSENDart;dinenENdout8位數(shù)據(jù)總線？2.8:3優(yōu)先編碼器GSlibraryieee;useieee.std_logic_1164.all;ENTITYpriencoderisPORT(din:INSTD_LOGIC_VECTOR(7downto0);ei:INSTD_LOGIC;yout:OUTSTD_LOGIC_VECTOR(2downto0);eo,gs:OUTSTD_LOGIC);ENDpriencoder;ARCHITECTUREcod74148OFpriencoderISBEGINPROCESS(ei,din)BEGINIF(ei='1')THENyout<="111";eo<='1';gs<='1';ELSE

IF(din(7)='0')THENyout<="000";eo<='1';gs<='0';ELSIF(din(6)='0')THENyout<="001";eo<='1';gs<='0';ELSIF(din(5)='0')THENyout<="010";eo<='1';····················································ELSIF(din(0)='0')THENyout<="111";eo<='1';gs<='0';ELSEyout<="111";eo<='0';gs<='1';ENDIF;ENDIF;ENDPROCESS;ENDcod74148;觸發(fā)器、寄存器、計數(shù)器、分頻器、節(jié)拍發(fā)生器、狀態(tài)機等。二、時序邏輯電路設(shè)計時鐘上升沿：（clock’eventandclock=‘1’）時鐘下降沿：（clock’eventandclock=‘0’）進程的敏感信號是時鐘信號，在進程內(nèi)部用if語句描述時鐘的邊沿條件。敏感信號表的特點：

1)敏感信號表中只有時鐘信號－－同步復(fù)位等。如：

process(clk)

begin

if(clk’eventandclk=‘1’)then

ifreset=‘1’thendata<=“00”;

elsedata<=in_data;

endif;

end

if;

endprocess;最先判斷時鐘同步復(fù)位同步復(fù)位2D觸發(fā)器2)敏感信號表中除時鐘外，還有其它信號－－異步操作例：

process(clk，reset)

begin

ifreset=‘1’thendata<=“00”;

elsif(clk’eventandclk=‘1’)thendata<=in_data;

endif;

endprocess;

最先判斷異步復(fù)位同步、異步區(qū)別：敏感信號表、語句順序?qū)τ谂袛鄷r鐘電路邊沿，后沒有“else”語句。2)計數(shù)器描述計數(shù)器(std_logic_vector)，要用到中間信號和標準的程序包：IEEE.STD_LOGIC_UNSIGNEDlibraryIEEE;use

IEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycounter10isPort

(clk:in

std_logic;load:in

std_logic;din:instd_logic_vector(3downto0);qout:outstd_logic_vector(3downto0)；

c:outstd_logic);endcounter10;例：異步置數(shù)(低有效）的10進制計數(shù)器。architectureartof

counter10

is

signal

temp:std_logic_vector(3downto0);beginprocess(clk,load,din)begin

if(load='0')then

temp<=din;

elsif(clk’eventandclk=‘1’)then

if(temp=“1001“)thentemp<="0000";

else

temp<=temp+1;

endif;

endif;endprocess;qout<=temp;c<='1‘whentemp=“1001”else‘0’;

endart;為描述計數(shù)過程，定義中間信號。--if(temp=9)then--whentemp=9elseprocess(clk,reset,din)

begin

if(load='0')then

temp<=din;elsif

(clk’eventandclk=‘1’)then

if(temp=9)thentemp<="0000";c<=‘1’;

else

temp<=temp+1;c<=‘0’;

endif;

endif;endprocess;qout<=temp;Endart

················if(clk’eventandclk=‘1’)then

if(temp=m-1)thentemp<="00···00";

else

temp<=temp+1;

endif;endif;endprocess;q<=temp;

c<='1‘whentemp=m-1else‘0’;例：六十進制（分、秒）計數(shù)器libraryIEEE;use

IEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entityclock60is

Port(clk:in

std_logic;clr:in

std_logic;s1:outstd_logic_vector(3downto0);s10:outstd_logic_vector(2downto0);co:out

std_logic);endclock60;architectureartof

clock60

is

signal

s1_temp:std_logic_vector(3downto0);

signals10_temp:std_logic_vector(2downto0);與一般二進制計數(shù)器不同，分個位十位顯示，為分、秒計數(shù)beginprocess(clk,clr)beginif(clr=‘1‘)thens1_temp<=“0000”;s10_temp<=“000”;elsif

(clk’eventandclk=‘1’)then

if(s1_temp=9)thens1_temp<="0000";

if(s10_temp=5)thens10_temp<=“000”;else

s10_temp<=s10_temp+1;

endif;else

s1_temp<=s1_temp+1;

endif;

endif;

endprocess;s1<=s1_temp;s10<=s10_temp;co<=‘1’when(s10_temp=5ands1_temp=9)

else‘0’;Endart;libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;ENTITYaddISPORT(clk,x,y:INSTD_LOGIC;qout:OUTSTD_LOGIC_VECTOR(2DOWNTO0);co:OUTSTD_LOGIC);ENDadd;ARCHITECTUREbehvOFaddIsSIGNALcon:std_logic_vector(1downto0);SIGNALtemp:std_logic_vector(2downto0);SIGNALm:integerrange7downto0;BEGINPROCESS(x,y)begincon<=x&y;caseconiswhen"00“=>m<=3;when"01"=>m<=4;when"10"=>m<=6;whenothers=>m<=7;ENDcase;

ENDprocess;?？煽赜嫈?shù)器（由輸入x,y控制）M=3,4,6,7PROCESS(clk,m)beginif(clk'eventandclk='1')thenif(temp=m-1)thentemp<="000";elsetemp<=temp+1;ENDIF;ENDIF;

ENDPROCESS;

qout<=temp;co<='1'whentemp=m-1else'0';ENDbehv;M=3,4,6,7例：設(shè)計5000分頻器libraryIEEE;use

IEEE.STD_LOGIC_1164.ALL;entityfpisPort

(clk:in

std_logic;clkout

:outstd_logic);endfp;architectureartof

fp

is

signaltemp:integer

range0to4999;Begin

process

(clk)

begin

if(clk’eventandclk=‘1’)then

if(temp=4999)thentemp<=0;elsetemp<=temp+1;

endif;endif;endprocess;clkout<='1'when(temp<2500)else'0';

endart;（占空比50％）例：8位環(huán)形移位寄存器（左、右移、異步置數(shù)）libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entityshfrtisPort

(clk,load,con:instd_logic;din:in

std_logic_vector(7downto0);qout

:outstd_logic_vector(7downto0));endshfrt;architectureartofshfrt

is

signalq_temp:std_logic_vector(7downto0);

beginprocess(clk,load,din)

begin

if

load=‘1’thenq_temp<=din;

elsif(clk’eventand

clk=‘1’)thenif

con=‘1’thenq_temp<=q_temp(6downto

0)&q_temp(7);

elseq_temp<=q_temp(0)&q_temp(7downto1);

endif;

endif;

Endprocess;qout<=q_temp;Endart;例：環(huán)型順序脈沖發(fā)生器(4位）libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;entityindexis

Port(clk,ld:in

std_logic;y

:outstd_logic_vector(3downto0));endindex;architectureartof

index

issignal

q:std_logic_vector(3downto0);beginprocess(clk)

begin

if(clk’eventandclk=‘1’)

then

ifld=‘0’thenq<=“1000”;

elseq<=q(0)&q(3downto1);

endif;

endif;

Endprocess;y<=q;

End

art;3)狀態(tài)機

用戶自定義數(shù)據(jù)類型利用用戶自定義數(shù)據(jù)類型－－枚舉類型實現(xiàn)。type數(shù)據(jù)類型名is

數(shù)據(jù)類型定義（枚舉）;

語法格式：綜合器自動實現(xiàn)枚舉類型元素的編碼typestatetype

is

(s0,s1,s2,s3);signalpresent_state,next_state:statetype;……typeweekis(sun,mon,tue,wed,thu,fri,sat);Signalday:week;……day<=sun;present_state<=S0;

狀態(tài)機整體描述結(jié)構(gòu)和輸出的描述

組合進程：描述狀態(tài)邏輯、輸出邏輯；時序進程：描述從次態(tài)到現(xiàn)態(tài)轉(zhuǎn)換；

——

兩段式有限狀態(tài)機

狀態(tài)轉(zhuǎn)移的描述CASE

現(xiàn)態(tài)IS

WHEN

表達式值1=>順序處理語句11；語句12；

……

WHEN表達式值3=>順序處理語句31；語句32;

ENDCASE；Moore型狀態(tài)機的描述LIBRARYIEEE;USE

IEEE.STD_LOGIC_1164.ALL;ENTITYmooreIS

PORT(clk,x:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDmoore;ARCHITECTUREbehvOFmooreIS

TYPE

StateIS(s0,s1,s2,s3);SIGNALcurrent_state,next_state:State;BEGIN第一進程，完成狀態(tài)轉(zhuǎn)換，必須飽含時鐘敏感信號REG:

PROCESS

(clk)

BEGIN

IF

(clk'EVENTandclk='1')THEN

current_state<=next_state;

ENDIF;

ENDPROCESS;COM:PROCESS

(current_state,x)

BEGIN

CASEcurrent_stateIS

WHENs0=>y<=‘0’;

IFx=‘0’THEN

next_state<=s0;

ELSE

next_state<=s1;

ENDIF;

WHENs1=>y<=‘1’;

IFx=‘0’THEN

next_state<=s2;

ELSE

next_state<=s1;

ENDIF;

WHENs2=>y<=‘0’;

IFx=‘0’THEN

next_state<=s3;

ELSE

next_state<=s2;END

if;

第二進程：輸出和狀態(tài)邏輯間關(guān)系，必須包含現(xiàn)態(tài)、輸入等敏感信號

WHENs3=>y<=‘0’;IFx=‘0’THEN

next_state<=s1;

ELSE

next_state<=s0;

ENDIF;ENDCASE;

ENDprocess;ENDbehy;摩爾型LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYmealyIS

PORT(clk,x:INSTD_LOGIC;y:OUTSTD_LOGIC);ENDmealy;ARCHITECTUREbehvOFmealyIS

TYPE

stateIS(s0,s1,s2,s3);

SIGNALcurrent_state,next_state:state;BEGIN

REG:

PROCESS(clk)

BEGIN

IF

(clk'EVENTandclk='1')THEN

current_state<=next_state;

ENDIF;

ENDPROCESS;Mealy型有限狀態(tài)機的設(shè)計1/0COM:PROCESS

(current_state,x)BEGIN

CASEcurrent_stateIS

WHENs0=>IFx=‘0’THENnext_state<=s0;y<=‘0’;

ELSE

next_state<=s1;

y<=‘0’;

ENDIF;

WHENs1=>IFx=‘0’THEN

next_state<=s0;

y<=‘0’;

ELSE

next_state<=s2;

y<=‘0’;

ENDIF;1/0WHENs2=>IFx=‘0’THEN

next_state<=s0;y<=‘0’;

ELSE

next_state<=s3;y<=‘0’;

ENDIF;

WHENs3=>IFx=‘0’THEN

next_state<=s0;y<=‘0’;

ELSE

next_state<=s3;y<=‘1’;

ENDIF;ENDcase;

ENDPROCESS;ENDbehv;1/05.5.4VHDL的層次化（結(jié)構(gòu)化）設(shè)計與元件例化(component)語句在多層次的設(shè)計中，高層次的設(shè)計模塊調(diào)用低層次的設(shè)計模塊，構(gòu)成模塊化的設(shè)計。重點描述模塊間的連接關(guān)系。由元件聲明、元件例化兩部分關(guān)鍵語句組成。被例化元件的來源：

VHDL設(shè)計實體；其它HDL設(shè)計實體；廠商提供的工藝庫中的元件、IP核。層次化設(shè)計的優(yōu)點：分工共享移植周期短一個元件是一段結(jié)構(gòu)完整的常用代碼，包括聲明，實體和結(jié)構(gòu)體，使用component可以使代碼具有層次化的結(jié)構(gòu)。1.元件聲明：在結(jié)構(gòu)體說明區(qū)中對所調(diào)用的低層次的實體模塊（名稱、端口類型等）聲明為元件。

2.元件例化：將低層次元件調(diào)用、安裝到當前層次。給出連接映射。COMPONENT元件名PORT

(端口名表)；ENDCOMPONENT

；例化名:低層元件名

PORTMAP(端口列表）;語法格式：語法格式：端口列表：低層端口名=>當前名稱（或，直接位置映射）一位全加器的原理圖

LIBRARYIEEE;--或門邏輯描述

USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2aIS

PORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);

END

or2a；

ARCHITECTUREart1OFor2aIS

BEGINc<=aORb;ENDart1;LIBRARYIEEE;--半加器描述USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_adderIS

PORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDadder;ARCHITECTUREart2OFadderis

BEGIN

so<=aXORb;co<=aANDb;ENDart2;必須與元件例化中的端口順序一致LIBRARYIEEE;--1位二進制全加器頂層設(shè)計描述

USE

IEEE.STD_LOGIC_1164.ALL;ENTITYf_adderIS

PORT(ain，bin，cin:INSTD_LOGIC;cout，sum:OUTSTD_LOGIC);

ENDf_adder;ARCHITECTUREart3OFf_adderIS

COMPONENTh_adder

PORT(a，b:INSTD_LOGIC;co，so:OUTSTD_LOGIC);ENDCOMPONENT；－－元件聲明

COMPONENTor2aPORT(a，b:INSTD_LOGIC;c:OUTSTD_LOGIC);

ENDCOMPONENT；

SIGNALd，e，f:STD_LOGIC;

BEGINu1:h_adderPORT

MAP(ain，bin，d，e);u2:h_adderPORT

MAP(a=>e，b=>cin，co=>f，so=>sum);u3:or2aPORT

MAP(d，f，cout);－－元件例化

ENDart3;VHDL舉例LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYcount4IS

PORT(clk,x:INSTD_LOGIC;qout:OUTSTD_LOGIC

_VECTOR(1DOWNTO0);y:OUTSTD_LOGIC);ENDcount4;ARCHITECTUREbehvOFcount4IS

TYPE

stateIS(s0,s1,s2,s3);

SIGNALc_state,n_state:state;BEGIN

REG:

PROCESS(clk)

BEGIN

IF

(clk'EVENTandclk='1')THEN

c_state<=n_state;

ENDIF;

ENDPROCESS;4進制格雷碼可逆計數(shù)器X=0時順時針000111100/11/1s0s1s2s30/00/00/01/01/01/0COM:PROCESS

(c_state,x)BEGIN

CASEc_stateIS

WHENs0=>qout<=“00”;

IFx=‘0’THENn_state<=s1;y<=‘0’;

ELSE

n_state<=s3;

y<=‘1’;

ENDIF;

WHENs1=>qout<=“01”;

IFx=‘0’THEN

n_state<=s2;

y<=‘0’;

ELSE

n_state<=s0;

y<=‘0’;

ENDIF;000111100/11/1s0s1s2s30/00/00/01/01/01/0WHENs2=>qout<=“11”;

IFx=‘0’THENn_state<=s3;y<=‘0’;

ELSE

n_state<=s1;y<=‘0’;

ENDIF;

WHENs3=>qout<=“10”;

IFx=‘0’THEN

n_state<=s0;y<=‘1’;ELSE

n_state<=s2;y<=‘0’;

ENDIF;ENDcase;

ENDPROCESS;