基于FPGA的智能電子搶答器的設(shè)計(jì) (2)課件

基于FPGA的智能電子搶答器的設(shè)計(jì)報(bào)告人:XXX學(xué)號(hào)：XXXXXX指導(dǎo)老師:XXX畢業(yè)設(shè)計(jì)答辯畢業(yè)設(shè)計(jì)答辯課題簡介：基于VHDL語言，并采用FPGA作為控制核心，設(shè)計(jì)一種四路智能電子搶答器，使其能夠?qū)崿F(xiàn)正確顯示最先搶答的選手號(hào)碼，對答題時(shí)間進(jìn)行l(wèi)00S的限時(shí)報(bào)警以及復(fù)位重新?lián)尨鸬墓δ?。具有電路簡單、操作方便、靈敏可靠等優(yōu)點(diǎn)。畢業(yè)設(shè)計(jì)答辯實(shí)施方案：利用VHDL硬件描述語言進(jìn)行編程，我的這個(gè)設(shè)計(jì)主要包括七個(gè)模塊：判斷模塊，鎖存模塊，轉(zhuǎn)換模塊，掃描模塊，片選模塊，定時(shí)報(bào)警模塊和譯碼模塊。編程完成后，用QuartersII軟件進(jìn)行編譯，驗(yàn)證正確后再進(jìn)行仿真。最后利用cyclone中的EP1C3T144C8制作成實(shí)際的系統(tǒng)進(jìn)行測試。畢業(yè)設(shè)計(jì)答辯片選信號(hào)產(chǎn)生模塊SEL--sel.vhdLIBRARYIEEE;USEIEEESTD_LOGIC_1164.ALL;ENTITYSELISPORT(CLK:INSTD_LOGIC;a:OUTINTEGERRANGE0TO7);ENDSEL;ARCHITECTURESEL_ARCOFSELIS

BEGINPROCESS(CLK)VARIABLEAA:INTEGERRANGE0TO7;BEGINIFCLK'EVENTANDCLK='1'THENAA:=AA+1;ENDIF;A<=AA;ENDPROCESS;ENDSEL_ARC;鎖存器模塊LOCKB--lockb.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYLOCKBISPORT(D1,D2,D3,D4:INSTD_LOGIC;CLK,CLR:INSTD_LOGIC;Q1,Q2,Q3,Q4,ALM:OUTSTD_LOGIC);ENDLOCKB;ARCHITECTURELOCK_ARCOFLOCKBISBEGINPROCESS(CLK)BEGINIFCLR='0'THENQ1<='0';Q2<='0';Q3<='0';Q4<='0';ALM<='0';ELSIFCLK'EVENTANDCLK='1'THENQ1<=D1;Q2<=D2;Q3<=D3;Q4<=D4;ALM<='1';ENDIF;ENDPROCESS;ENDLOCK_ARC;畢業(yè)設(shè)計(jì)答辯轉(zhuǎn)換模塊CH41A--ch41a..vhd

LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH41AISPORT(D1,D2,D3,D4:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCH41A;ARCHITECTURECH41_ARCOFCH41AISBEGINPROCESS(D1,D2,D3,D4)VARIABLETMP:STD_LOGIC_VECTOR(3DOWNTO0);BEGINTMP:=D1&D2&D3&D4;CASETMPISWHEN"0111"=>Q<="0001";WHEN"1011"=>Q<="0010";WHEN"1101"=>Q<="0011";WHEN"1110"=>Q<="0100";WHENOTHERS=>Q<="1111";ENDCASE;ENDPROCESS;ENDCH41_ARC;3選1模塊CH31A--ch31a.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH31AISPORT(SEL:INSTD_LOGIC_VECTOR(2DOWNTO0);D1,D2,D3:INSTD_LOGIC_VECTOR(3DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCH31A;ARCHITECTURECH31_ARCOFCH31AIS

BEGINPROCESS(SEL,D1,D2,D3)BEGINCASESELISWHEN"000"=>Q<=D1;WHEN"001"=>Q<=D2;WHEN"111"=>Q<=D3;WHENOTHERS=>Q<="1111";ENDCASE;ENDPROCESS;ENDCH31_ARC;畢業(yè)設(shè)計(jì)答辯倒計(jì)時(shí)模塊COUNT

--count.vhdLIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTISPORT(CLK,EN:INSTD_LOGIC;H,L:OUTSTD_LOGIC_VECTOR(3DOWNTO0);SOUND:OUTSTD_LOGIC);ENDCOUNT;ARCHITECTURECOUNT_ARCOFCOUNTISBEGINPROCESS(CLK,EN)VARIABLEHH,LL:STD_LOGIC_VECTOR(3DOWNTO0);BEGINIFCLK'EVENTANDCLK='1'THENIFEN='1'THEN;

IFLL=0ANDHH=0THENSOUND<='1';ELSIFLL=0THENLL:="1001";HH:=HH-1;ELSELL:=LL-1;ENDIF;ELSESOUND<='0';HH:="1001";LL:="1001";ENDIF;ENDIF;H<=HH;L<=LL;ENDPROCESS;ENDCOUNT_ARC畢業(yè)設(shè)計(jì)答辯搶答器系統(tǒng)原理圖畢業(yè)設(shè)計(jì)答辯在QuartersII中對程序生成模塊，連接電路圖，可得到搶答器的頂層原理圖。畢業(yè)設(shè)計(jì)答辯頂層原理圖畢業(yè)設(shè)計(jì)答辯Feng搶答判斷模塊：Lockb鎖存模塊：畢業(yè)設(shè)計(jì)答辯Ch31a掃描模塊：Ch41a顯示轉(zhuǎn)換模塊：畢業(yè)設(shè)計(jì)答辯Count定時(shí)模塊：Sel片選模塊：畢業(yè)設(shè)計(jì)答辯結(jié)論本文介紹了基于FPGA的智