第6講vhdl語言實(shí)際舉例

VHDL設(shè)計舉例VHDL設(shè)計舉例數(shù)據(jù)選擇器設(shè)計半加器設(shè)計時鐘邊沿描述—觸發(fā)器、寄存器設(shè)計3-8譯碼器、七段顯示譯碼器設(shè)計ROM設(shè)計半減器和或門構(gòu)成全減器WHEN語句實(shí)現(xiàn)二路數(shù)據(jù)選擇器ENTITYmux21aIS

PORT(a,b.:INBIT;

s:INBIT;

Y:OUTBIT);

END

ENTITYmux21a;ARCHITECTUREoneOFmux21aIS

BEGIN

y<=a;WHENs=‘0’ELSEb;

ENDmux21a;數(shù)據(jù)選擇器abysmux21a實(shí)體：描述電路器件的外部情況以及各信號端口的基本性質(zhì)結(jié)構(gòu)體：描述電路器件的內(nèi)部邏輯功能或電路結(jié)構(gòu)LIBRARYieee;

USEieee.std_logic_1164.all;WHEN語句實(shí)現(xiàn)二路數(shù)據(jù)選擇器ENTITYmux21aIS

PORT(a,b.:INBIT;

s:INBIT;

Y:OUTBIT);

END

ENTITYmux21a;ARCHITECTUREoneOFmux21aIS

BEGIN

y<=a;WHENs=‘0’ELSEyb;

ENDmux21a;WHEN語句的一般形式為：

目標(biāo)<=表達(dá)式WHEN賦值條件ELSE目標(biāo)<=表達(dá)式WHEN賦值條件ELSE……表達(dá)式;數(shù)據(jù)選擇器WHEN語句為并行語句abysmux21aENTITYmux21aIS

PORT(a,b.:INBIT;

s:INBIT;

Y:OUTBIT);

END

ENTITYmux21a;ARCHITECTUREoneOFmux21aIS

BEGIN

PROCESS(a,b,s)

BEGIN

IFs=‘0’THEN

y<=a;ELSEy<=b;

ENDIF;

ENDPROCESS;

ENDmux21a;abysmux21aIF語句實(shí)現(xiàn)二選一數(shù)據(jù)選擇器IF語句的一般形式為：

IF<條件>THEN

<語句>；

ELSIF<條件>THEN

<語句>；

ELSIF<條件>THEN

<語句>；

ELSE

<語句>；ENDIF;數(shù)據(jù)選擇器用與或非邏輯實(shí)現(xiàn)二選一數(shù)據(jù)選擇器ENTITYmux21aIS

PORT(a,b.:INBIT;

s:INBIT;

Y:OUTBIT);

ENDmux21a;ARCHITECTUREoneOFmux21aISSIGNALd,e:BIT;

BEGIN

d<=aAND(NOTs);e<=bANDs;Y<=dORe;ENDmux21a;數(shù)據(jù)選擇器BEGIN

Y<=(aAND(NOTs))OR(bANDs);ARCHITECTUREsels_arcOFselsISBEGIN

WITHsSELECT

out1<=d0WHEN0,

d1WHEN1,

d2WHEN2,

d3WHEN3;

ENDsels_arc;四路數(shù)據(jù)選擇器說明WITH語句用法ENTITYselsIS

PORT(d0,d1,d2,d3:INBIT;

s:ININTEGERRANGE0TO3;

out1:OUTBIT);

ENDsels;d0d1d2d3sout1sels數(shù)據(jù)選擇器

選擇信號賦值語句的一般形式如下：

WITH<表達(dá)式>SELECT

<對象><=<信號1>WHEN<分支1>,

<信號2>WHEN<分支2>,

<信號n>WHEN<分支n>;數(shù)據(jù)選擇器LIBRARYieee;

USEieee.std_logic_1164.all;

ENTITYh_adderIS

PORT(a,b:INSTD_LOGIC;

co,so:OUTSTD_LOGIC);

ENDh_adder;CASE條件語句實(shí)現(xiàn)半加器半加器absoh_addercoABSC0000011010101101ARCHITECTUREoneOFh_adderIS

SIGNALabc:STD_LOGIC_VECTOR(1DOWNTO0);BEGIN

abc<=a&b;

BEGIN

PROCESS(abc)

BEGINCASEabcIS

WHEN“00”=>so<=‘0’;co<=‘0’’;

WHEN“01”=>so<=‘1’;co<=‘0’’;

WHEN“10”=>so<=‘1’;co<=‘0’’;

WHEN“11”=>so<=‘0’;co<=‘1’’;WHENOTHERS=>so<=‘0’;co<=‘0’’;ENDPROCESS;

ENDh_adder;ABSC0000011010101101CASE條件語句實(shí)現(xiàn)半加器用CASE語句應(yīng)該注意三個問題：（1）關(guān)鍵字WHEN的數(shù)量不作限制，但不容許兩個語句用一個值；（2）所有WHEN后面的值在CASE語句中合起來的值是值域中的全部；（3）WHEN語句的次序可以任意排定。CASE語句的一般形式：CASE<表達(dá)式>IS

WHEN<值>＝><語句>；

WHEN<值>|<值>＝><語句>；

……

WHENOTHERS＝><語句>；

ENDCASE;CASE語句的相關(guān)說明ENTITYDFF1IS

PORT(clk:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTSTD_LOGIC);

ENDDFF1;

ARCHITECTUREDFF_arcOFDFF1IS

BEGIN時鐘邊沿描述D觸發(fā)器說明時鐘邊沿描述的用法ENDDFF1_arc;PROCESS(clk)

BEGIN

IFclk’EVENTANDclk=‘1’;

THENQ<=D;ENDIF;

ENDPROCESS;PROCESS

BEGIN

WAITUNTILclk=‘1’;

Q<=D;

ENDPROCESS;ENTITYregIS

PORT(d,clk:INBIT;

q1,q2:OUTBIT);

ENDreg;

ARCHITECTUREreg_arcOFregIS

BEGINPROCESS

BEGIN

WAITUNTILclk=‘1’;

q1<=d;

ENDPROCESS;PROCESS

BEGIN

WAITUNTILclk=‘0’;q2<=d;

ENDPROCESS;ENDreg_arc;進(jìn)程行為語句之間是并行關(guān)系，進(jìn)程行為語句內(nèi)部是順序關(guān)系。VHDL的每個結(jié)構(gòu)體中可以有多個進(jìn)程行為語句。它的關(guān)鍵之處是：時鐘邊沿描述D觸發(fā)器說明時鐘邊沿描述的用法時鐘邊沿描述ENTITYregIS

PORT(clk:INSTD_LOGIC;D:INSTD_LOGIC_VECTOR(7DOWNTO0);Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));

ENDreg;

ARCHITECTUREreg_arcOFregIS

BEGIN8位通用寄存器ENDreg_arc;PROCESS(clk)

BEGIN

IFclk’EVENTANDclk=‘1’;

THENQ<=D;

ENDPROCESS;3-8通用譯碼器程序的例子，說明進(jìn)程語句如何工作。LIBRARYieee;

USEieee.std_logic_1164.all;

USEieee.std_logic_arith.all;

ENTITYdecoderIS

PORT(a,b,c:INSTD_LOGIC;G1,G2a,G2b:INSTD_LOGIC;

Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDdecoder;ARCHITECTUREdecoder_arcOFdecoderIS

SIGNALindata:STD_LOGIC_VECTOR(2DOWNTO0);

BEGIN

indata<=a&b&cPROCESS(indata,G1,G2a,G2b)

BEGINY0......Y7ABCG1selsG2aG2bIF(G1=1andG2a=0andG2b=0)

CASEindataIS

WHEN“000”=>Y<=“11111110”;WHEN“001”=>Y<=“11111101”;WHEN“010”=>Y<=“11111011”;WHEN“011”=>Y<=“11110111”;

WHEN“100”=>Y<=“11101111”;

WHEN“101”=>Y<=“11011111”;

WHEN“110”=>Y<=“10111111”;WHEN“111”=>Y<=“01111111”;WHENOTHERS=>Y<=NULL;

ENDCASE;ELSEY<=“11111111”;

ENDIF;

ENDPROCESS;

ENDdecoder_arc;ARCHITECTURErom_arcOFromIS

BEGIN

PROCESS(cs,x1,x2,x3,x4)

VARIABLEn:NATURAL

RANGE0TO15;

CONSTANTrom0:std_logic_vector(0TO15):=“0101010101010101”;

CONSTANTrom1:std_logic_vector(0TO15):=“0011001100110011”;

CONSTANTrom2:std_logic_vector(0TO15):=“0000111100001111”;

CONSTANTrom3:std_logic_vector(0TO15):=“0000000011111111”;一維數(shù)組實(shí)現(xiàn)16×4的ROM。LIBRARYieee;USEieee.std_logic_1164.all;ENTITYromISPORT(cs,x1,x2,x3,x4:INstd_logic;d0,d1,d2,d3:OUTstd_logic);ENDrom;romcsx1x2x3x4d0d1d2d3rom0（0）=0rom0（15）=1

BEGINROM

IFcs=‘1’THEN

n:=0;

IFx1=‘1’THENn:=n+1;ENDIF;

IFx2=‘1’THENn:=n+2;ENDIF;

IFx3=‘1’THENn:=n+4;ENDIF;

IFx4=‘1’THENn:=n+8;ENDIF;

d0<=rom0(n)AFTER10ns;

d1<=rom1(n)AFTER10ns;

d2<=rom2(n)AFTER10ns;

d3<=rom3(n)AFTER10ns;

ELSE

d0<=‘Z’AFTER10ns;

d1<=‘Z’AFTER10ns;

d2<=‘Z’AFTER10ns;

d3<=‘Z’AFTER10ns;

ENDIF;

ENDPROCESS;

ENDrom_arc;用計算n來定位地址。將地址n中的4位數(shù)據(jù)送到輸出d0～d3。如果芯片不使能，則將高阻送到輸出d0～d3。例：用VHDL結(jié)構(gòu)描述設(shè)計一全減器，全減器可由兩個半減器和一個或門組成。首先用VHDL的行為描述設(shè)計半減器：ENTITYhalfsubIS

PORT(A,B:INBIT;

T,C:OUTBIT);

ENDhalfsub;

PROCESS(A,B)

BEGIN

T<=AXORBAFTER10ns;

C<=(NOTA)ANDBAFTER10ns;

ENDPROCESS;ARCHITECTUREhalfsub_arcOFhalfsubIS

BEGINENDhalfsub_arc;一定記住輸入、輸出端口的順序。下面再將或門的VHDL程序描述如下：ARCHITECTUREorgate_arcOForgateIS

BEGINO1<=A1ORB1;ENDorgate_arc;下面將兩個半減器，一個或門的端口，通過定義一些中間信號將其連接起來形成VHDL的結(jié)構(gòu)描述。ENTITYorgateIS

PORT(A1,B1:INBIT;O1:OUTBIT);ENDorgate;一定記住輸入、輸出端口的順序。在下面舉的全減器例子里可以看到定義了中間信號temp_T,temp_c1和temp_c2