第四章vhdl(6)組合邏輯電路

第4章組合邏輯電路設(shè)計(jì)

組合電路在任一時(shí)刻的輸出僅取決于該時(shí)刻電路的輸入，與電路原來的狀態(tài)無關(guān)，即無存儲(chǔ)部件。4.5組合邏輯電路基本邏輯：與、或、非、與非、或非、異或編／譯碼器與選擇器加（減）法器、求補(bǔ)器三態(tài)門及總線緩沖器奇偶校驗(yàn)電路、多人表決器、比較器4.5.1基本邏輯4.5.2譯碼器/編碼器/選擇器4.5.3加法器/求補(bǔ)器4.5.4三態(tài)門及總線緩沖器4.5.5奇偶校驗(yàn)電路/多人表決器/比較器4.5.1基本邏輯直接用邏輯運(yùn)算符實(shí)現(xiàn)用if、case等語句描述例：libraryieee;useieee.std_logic_1164.all;entityn_andisport(a,b:instd_logic;c:outstd_logic);endn_and;architecturertlofn_andisbeginc<=anandb;endrtl;例：architecturertlofexmisbeginProcess(a,b)begintmp<=a&b;casetmpiswhen“00”=>y<=‘1’;when“01”=>y<=‘0’;when“10”=>y<=‘0’;when“11”=>y<=‘0’;whenothers=>y<=‘Z’;endcase;endprocess;endrtl;分析實(shí)現(xiàn)的邏輯4.5.2譯碼器/編碼器/選擇器

1.譯碼器

3-8譯碼器2-4譯碼器七段顯示譯碼器地址譯碼器特殊譯碼器：一般譯碼器：七段顯示譯碼器：七段顯示譯碼器是對(duì)一個(gè)4位二進(jìn)制數(shù)進(jìn)行譯碼，并在七段數(shù)碼管上顯示出相應(yīng)的十進(jìn)制數(shù)或十六進(jìn)制數(shù)。地址譯碼器：在計(jì)算機(jī)和微處理器系統(tǒng)是很重要的，是數(shù)字系統(tǒng)中最典型的CPLD應(yīng)用。……ARCHITECTUREART3OFDECODERISBEGIND_OUT(0)<=‘1’WHEND_IN="000"ELSE‘0’；D_OUT(1)<=‘1’WHEND_IN="001"ELSE‘0’；D_OUT(2)<=‘1’WHEND_IN="010"ELSE‘0’；D_OUT(3)<=‘1’WHEND_IN="011"ELSE‘0’；D_OUT(4)<=‘1’WHEND_IN="100"ELSE‘0’；D_OUT(5)<=‘1’WHEND_IN="101"ELSE‘0’；D_OUT(6)<=‘1’WHEND_IN="110"ELSE‘0’；D_OUT(7)<=‘1’WHEND_IN="111"ELSE‘0’；ENDART3；

練習(xí)2-4譯碼器1)3-8譯碼器2)七段顯示譯碼電路process(d)begincasediswhen"0000"=>y<="0111111";when"0001"=>y<="0000110";when"0010"=>y<="1011011";when"0011"=>y<="1001111";when"0100"=>y<="1100110";when"0101"=>y<="1101101";when"0110"=>y<="1111101";when"0111"=>y<="0000111";when"1000"=>y<="1111111";when"1001"=>y<="1101111";whenothers=>y<="0000000";endcase;endprocess;七段譯碼如果譯碼功能由共陰轉(zhuǎn)為共陽只需對(duì)輸出做一個(gè)取反，不用重新譯碼3）地址譯碼器例如：一個(gè)微處理器存儲(chǔ)空間0000H---FFFFH,分為5部分，它們的地址分配如下：DRAM：0000H—DFFFH；I/O：E000H—E7FFH；備用：E800H---EFFFH；ROM1：F000H—F7FFH；ROM2：F800H—FFFFH；輸入為16位地址，輸出4個(gè)片選信號(hào)低電平有效PROCESS(address)BeginIfaddress<=x”dfff”thenDRAM<=‘0’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘1’;Elsifaddress>=x”e000”andaddress<=x”e7ff”thenDRAM<=‘1’;IO<=‘0’;ROM1<=‘1’;ROM2<=‘1’;Elsifaddress>=x”f000”andaddress<=x”f7ff”thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘0’;ROM2<=‘1’;Elsifaddress>=x”f800”thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘0’;Endif;Endprocess;A15A14A13A12A11A10~A0000000…0DRAM：0000H—DFFFH；110111…1111000…0I/O：E000H—E7FFH；111001…1111010…0備用：E800H—EFFFH；111011…1111100…0ROM1：F000H—F7FFH；111101…1111110…0ROM2：F800H—FFFFH；111111…1

A15~A11可區(qū)別地址，用最少地址線譯碼描述，輸入僅為A15~A11PROCESS(A15,A14,A13,A12,A11)BeginIf(A15andA14andA13)=‘0’

thenDRAM<=‘0’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘1’;ElsifA13=‘1’andA12=‘0’andA11=‘0’thenDRAM<=‘1’;IO<=‘0’;ROM1<=‘1’;ROM2<=‘1’;ElsifA13=‘1’andA12=‘1’andA11=‘0’thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘0’;ROM2<=‘1’;ElsifA13=‘1’andA12=‘1’andA11=‘1’thenDRAM<=‘1’;IO<=‘1’;ROM1<=‘1’;ROM2<=‘0’;Endif;Endprocess;2.編碼器生活中常用十進(jìn)制數(shù)及文字、符號(hào)等表示事物數(shù)字電路只能以二進(jìn)制信號(hào)工作用二進(jìn)制代碼表示文字符號(hào)等特定對(duì)象的過程，稱為編碼普通編碼器：任何時(shí)刻只允許輸入一個(gè)有效編碼請(qǐng)求信號(hào)，否則輸出將發(fā)生混亂優(yōu)先編碼器：允許同時(shí)輸入兩個(gè)以上的有效編碼請(qǐng)求信號(hào)，只對(duì)其中優(yōu)先權(quán)最高的一個(gè)進(jìn)行編碼優(yōu)先級(jí)別的高低由設(shè)計(jì)者根據(jù)輸入信號(hào)的輕重緩急情況而定。使用case語句沒有優(yōu)先級(jí)使用if、when_else語句帶有優(yōu)先級(jí)1)8線-3線普通編碼器（教材p83)2)用if_then_elsif_else實(shí)現(xiàn)優(yōu)先權(quán)編碼器libraryieee;useieee.std_logic_1164.all;entitypriorityisport(d:instd_logic_vector(7downto0);q:outstd_logic_vector(2downto0));endpriority;architectureoneofpriorityisbeginprocess(d)beginifd(0)='0'thenq<="111";elsifd(1)='0'thenq<="110";elsifd(2)='0'thenq<="101";elsifd(3)='0'thenq<="100";elsifd(4)='0'thenq<="011";elsifd(5)='0'thenq<="010";elsifd(6)='0'thenq<="001";elseq<="000";endif;endprocess;endone;2)when_else實(shí)現(xiàn)優(yōu)先權(quán)編碼器…….ARCHITECTUREART1OFENCODERISBEGINy<="111"WHENH=‘1’ELSE"110"WHENG=‘1’ELSE"101"WHENF=‘1’ELSE"100"WHENE=‘1’ELSE "011"WHEND=‘1’ELSE"010"WHENC=‘1’ELSE"001"WHENB=‘1’ELSE"000"WHENA=‘1’ELSE"XXX"；ENDART1;3.選擇器

選擇器常用于信號(hào)的切換四選一選擇器：4個(gè)信號(hào)輸入端2個(gè)信號(hào)選擇端1個(gè)信號(hào)輸出端

當(dāng)輸入不同的選擇信號(hào)時(shí)，就可以使4個(gè)輸入中某個(gè)相應(yīng)的輸入信號(hào)與輸出端接通。2選1ENTITYmux21ISPORT(d0,d1,sel:INBIT;q:OUTBIT);ENDmux21;ARCHITECTUREconnectOFmux21ISSIGNALtmp1,tmp2,tmp3:BIT;BEGIN;tmp1<=d0ANDsel;tmp2<=d1AND(NOTsel);tmp3<=tmp1ORtmp2;q<=tmp3;ENDconnect;

4.5.3加法器/求補(bǔ)器半加器全加器多位加法器求補(bǔ)器：對(duì)二進(jìn)制數(shù)進(jìn)行求補(bǔ)碼運(yùn)算libraryieee;useieee.std_logic_1164.all;entityfadderisport(a,b,cin:instd_logic;sum,cout:outstd_logic);endfadder;architecturertloffadderisbeginsum<=axorbxorcin;cout<=(aandb)or(aandcin)or(bandcin);endrtl;半加器（略）一位全加器CoutSum

baCin

CoutSum

baCinCoutSum

baCinCoutSum

baCincoutsum(3)sum(2)sum(1)sum(0)

b(3)a(3)b(2)a(2)b(1)a(1)b(0)a(0)cin四位加法器：libraryieee;useieee.std_logic_1164.all;entityadder4isport(a,b:instd_logic_vector(0to3);cin:instd_logic;cout:outstd_logic;sum:outstd_logic_vector(0to3));endadder4;architectureexmofadder4iscomponentfadderport(a,b,cin:instd_logic;sum,cout:outstd_logic);endcomponent;signalc:std_logic_vector(0to4);beginc(0)<=cin;gen:foriin0to3generateadderx:fadderportmap(a(i),b(i),c(i),sum(i),c(i+1));endgenerate;cout<=c(4);endexm;求補(bǔ)器libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitybuisport(a:instd_logic_vector(7downto0);b:outstd_logic_vector(7downto0));endbu;architecturertlofbuisbeginprocess(a)beginifa(7)=‘1’thenb<=nota+’1’;elseb<=a;endif;endprocess;endrtl;4.5.4三態(tài)門及總線緩沖器三態(tài)門數(shù)據(jù)輸入控制輸入 數(shù)據(jù)輸出din endoutX 0 Z0 1 01 1 1總線緩沖器由多個(gè)三態(tài)門組成，數(shù)據(jù)總線是幾位就有幾個(gè)三態(tài)門

緩沖器一般分為兩種：單向總線緩沖器雙向總線緩沖器三態(tài)門libraryieee;useieee.std_logic_1164.all;entitythreeisport(a,en:instd_logic;y:outstd_logic);endthree;architecturebhvofthreeisbeginprocess(a,en)beginifen='1'theny<=a;elsey<='Z';endif;endprocess;endbhv;8位雙向總線緩沖器LIBRARYieee;USEieee.std_logic_1164.all;ENTITYtri_bigateISPORT(a,b:INOUTstd_logic_vector(7downto0); en，dr:INstd_logic）;ENDtri_bigate;ARCHITECTURErtlOFtri_bigateISSignalaout,bout:std_logic_vector(7downto0);BEGINprocess(a,en,dr)beginif(en=‘1')and(dr=‘1’)thenbout<=a;elsebout<="ZZZZZZZZ";endif; b<=bout;endprocess；process(b,en,dr)beginif(en=‘1')and(dr=‘0’)thenaout<=b;elseaout<="ZZZZZZZZ";endif; a<=aout;endprocess;endrtl;

RTL不用aout和bout中間信號(hào)的RTL4.5.5奇偶校驗(yàn)電路/多人表決器/比較器1.奇偶校驗(yàn)電路具體程序見前面章節(jié)

另一種實(shí)現(xiàn)方式：將輸入的8位二進(jìn)制數(shù)用四位二進(jìn)制數(shù)進(jìn)行計(jì)數(shù)，判斷最低位，若為‘1‘，則為奇數(shù)；若為‘0‘，則為偶數(shù)。2.七人表決器libraryieee;useieee.std_logic_1164.all;entityvote7isport(a:instd_logic_vector(0to6);lg,lr:outstd_logic);end;architecturebhvofvote7issignalpass:integerrange0to10;begin

process(a)variabletmp1:integerrange0to10;begintmp1:=0;foriin0to6loopifa(i)='1'thentmp1:=tmp1+1;elsetmp1:=tmp1+0;endif;endloop;pass<=tmp1;endprocess;lg<='1'whenpass>=4else'0';lr<='1'whenpass<4else'0';endbhv;

LIBRARYieee;USEieee.std_logic_1164.all;entitybj7isport(a0,a1,a2,a3,a4,a5,a6:instd_logic;y:outstd_logic);endbj7;architectureaofbj7isfunctionsum(a,b,c:std_logic)returnstd_logicisbeginreturn(axorbxorc);endsum;functioncout(a,b,c:std_logic)returnstd_logicisbeginreturn((aandb)or(aandc)or(bandc));endcout;signalc:std_logic_vector(0to2);signals:std_logic_vector(0to2);begin--s(0)<=sum(a0,a1,a2);--s(1)<=sum(a3,a4,a5);--s(2)<=sum(s(0),s(1),a6);--c(0)<=cout(a0,a1,a2);--c(1)<=cout(a3,a4,a5);--c(2)<=cout(s(0),s(1),a6);--c(3)<=cout(c(0),c(1),c(2));--y<=c(3);s(0)<=sum(a0,a1,a2);s(1)<=sum(a3,a4,'0');s(2)<=sum(a5,a6,'0');c(0)<=cout(a0,a1,a2);c(1)<=cout(a3,a4,'0');c(2)<=cout(a5,a6,'0');y<=cout(c(0),c(1),c(2))or(sum(c(0),c(1),c(2))andcout(s(0),s(1),s(2)));enda;3.三人表決器（方法一行為描述方式)ENTITYmajISPORT(a,b,c:INBIT;m:OUTBIT);ENDmaj;ARCHITECTUREbhvOFmajISBEGINPROCESS(a,b,c)CONSTANTlookuptable:BIT_VECTOR