DDRSDRAM基礎(chǔ)知識(shí)完整版

DRAMBasicKnowledge

SummaryHulinCao–caohulin@DRAMBasicKnowledgeDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMBasicKnowledgeDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMDeviceArchitectureTypicalDRAMDeviceArchitectureSimple:1T-1CDatalosseswhenreadorover-timeDRAMDeviceArchitectureDataWidthofDRAMDeviceAlsothedatawidthofeachbankEachDRAMdevicewillhaveseveralbanksCont’dDRAMDeviceArchitectureBank?Rank?Channel?Cont’dDRAMDeviceArchitectureBankCont’dDRAMDeviceArchitectureRankCont’dDRAMDeviceArchitectureChannelCont’dDRAMDeviceArchitectureOverviewofBank,Rank,ChannelCont’dDRAMDeviceArchitectureExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspaceChannel0DIMM0Rank0MappedtoDRAMDeviceArchitectureExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspaceRank0Chip0Chip1Chip7<0:7><8:15><56:63>Data<0:63>8BRow0Col0...8BDRAMDeviceArchitectureExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspace<0:7><8:15><56:63>Data<0:63>8B8B8BRank0Chip0Chip1Chip7Row0Col1...DRAMDeviceArchitectureExample:TransferaCacheBlockCont’d0xFFFF…F0x000x40...64BcacheblockPhysicalmemoryspace<0:7><8:15><56:63>Data<0:63>8B8BRank0Chip0Chip1Chip7Row0Col1...A64Bcacheblocktakes8I/Ocyclestotransfer.Duringtheprocess,8columnsarereadsequentially.DRAMBasicKnowledgeDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMAccessFlowDRAMAccessFlowOverviewDRAMAccessFlowDifferentialSenseAmplifier–RowBufferCont’dDRAMAccessFlowCircuitsofDifferentialSenseAmplifierCont’dDRAMAccessFlowReadAccessStep1–WordLineSelectCont’dDRAMAccessFlowReadAccessStep2–SenseAmplifierCont’dDRAMAccessFlowReadAccessStep3–RestoreCont’dDRAMAccessFlowReadAccessStep4–Pre-chargeCont’dDRAMAccessFlowSenseAmplifierVoltageWaveform–ReadFlowCont’dDRAMAccessFlowWriteAccessFlowCont’dDRAMBasicKnowledgeDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommands&TimingParametersDRAMCommandSchedulePageClosePageOpenBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMBasicCommandsKeyTimingParametersParameterDescriptiontRCDRowtoColumncommand

DelayTimeintervalbetweenrowaccesscommandanddatareadatsenseamplifierstRASRowAccess

StrobeTimeintervalbetweenrowaccesscommandanddatarestorationinDRAMarraytCASColumnAccessStrobeTimeintervalbetweencolumnaccesscommandanddatareturnbyDRAMdevicetRPRow

PrechargetimeTimeintervalthatittakesforprechargeandreadyforanotherrowaccesstWRWriteRecoverytimeMinimumtimeintervalbetweenwriteburstandprecharge,restoredatatocelltRCRowCycletimeTimeintervalbetweenaccessestodifferentrowsinagivenbanktRFCRefreshCycletimeTimeintervalbetweenrefreshcommandandactivationcommandDRAMBasicCommandsRowAccessCommand–ActivationCont’dDRAMBasicCommandsColumnReadCommandCont’dDRAMBasicCommandsColumnWriteCommandCont’dDRAMBasicCommandsPrechargeCommandCont’dDRAMBasicCommandsRefreshCommandCont’dDRAMBasicCommandsMoreaboutDRAMRefreshThememorycontrollerneedstorefresheachrowperiodicallytorestorechargeReadandcloseeachroweveryNmsTypicalN=64msDownsideofDRAMRefreshPowerConsumePerformancedegradationRefreshratelimitsDRAMcapacityscalingCont’dDRAMBasicCommandsMoreaboutDRAMRefreshRefreshMethodBurstrefreshDistributedrefreshCont’dDRAMBasicCommandsMoreaboutDRAMRefreshCont’dDRAMBasicCommandsMoreaboutDRAMRefreshCont’dDRAMBasicCommandsDRAMRefreshinLPDDRxTCSRTemperatureCompensatedSelfRefreshEmbeddedtemperaturesensor,adjustrefreshperiodbasedontemperature (AlsoAdoptedinDDR4)PASRPartialArraySelfRefreshOnlyusepartoftheDRAMtosavepowerCont’dDRAMBasicCommandsAReadCycleCont’dDRAMBasicCommandsPowerConsumeinDRAMReadCycleCont’dDRAMBasicCommandsPowerRelatedTimingParameters–tRRDtRRD:RowtoRowactivationDelay,differentbankWillaffectDRAMcommandschedulingCont’dDRAMBasicCommandsPowerRelatedTimingParameters–tFAWtFAW:FourBankActivationWindowWillaffectDRAMcommandschedulingCont’dDRAMBasicCommandsThevalueoftRRDandtFAWisPageSizeRelatedExample:1GbitDDR2SDRAMdevicefromMicronCont’dDRAMBasicCommandsTheTrendoftRRDandtFAWCont’dDRAMBasicCommandstRRDandtFAWinDDR4Cont’dDRAMBasicKnowledgeDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageHit/MissPageOpen/ClosePolicyBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMCommandSchedulePage(RowBuffer)Hit/MissPageHit

NextRead/WriteAccessisinthesamebank&samerow AccessFlow:

Read/WriteCommand DataTransaction

PageMiss NextRead/WriteAccessisinthesamebank&differentrow AccessFlow:

Prechargetothecurrentrow Activenextrow Read/WriteCommand DataTransactionCont’dDRAMCommandSchedulePage(RowBuffer)Hit/MissDemoCont’dRowBuffer(Row0,Column0)RowdecoderColumnmuxRowaddress0Columnaddress0DataRow0Empty(Row0,Column1)Columnaddress1(Row0,Column85)Columnaddress85(Row1,Column0)HITHITRowaddress1Row1Columnaddress0CONFLICT!ColumnsRowsAccessAddress:DRAMCommandSchedulePageOpenKeeptherowopenafteranaccessNextaccessmightneedthesamerowrowhitNextaccessmightneedadifferentrowrowconflict,wastedenergyPageCloseClosetherowafteranaccess(ifnootherrequestsalreadyintherequestbufferneedthesamerow)NextaccessmightneedadifferentrowavoidarowconflictNextaccessmightneedthesamerowextraactivatelatencyCont’dDRAMCommandScheduleBankInterleaveLowtimecostwhenswitchbetweendifferentbankUsecertainaddressmappingtoincreasebankinterleaveAddressMappingExample:Row:Bank:ColumnCommandReorderReorderDRAMcommandstoimplementbankinterleaveandincreasepagehitrateReorderreadandwriteaccesscommandsGivereadcommandahigherpriorityReorderread/writecommandqueuetoincreasepagehitrate&bankinterleaveCont’dDRAMCommandScheduleExampleofBankInterleaveandCommandReorderCont’dDRAMCommandSchedulePerformanceAnalyzeofSchedulePolicyPerformanceTestScenarioDual-Core,DDR266,4ranksperchannelWeb-Serverbenchmark(Figure1)Read:Write–2:1;RandomAddress(Figure2,3)SchedulePolicyMC-A0 :Open,NoBank/RankInterleave,In-OrderMC-A1 :MC-AwithRankInterleaveMC-A2 :MC-AwithBankInterleaveandCloseMC-B0 :Close,Bank/RankInterleave,In-OrderMC-B1 :MC-B0withRe-Order,givereadcommandhigherprioritybutread/writecommandqueueinorderMC-B2 :MC-B1withRe-OrderinRead/WriteCommandQueueNote:

Theordermeanstheorderofread/writeaccessCont’dDRAMCommandSchedulePerformanceAnalyzeofSchedulePolicyCont’dWeb-ServerbenchmarkDRAMCommandSchedulePerformanceAnalyzeofSchedulePolicyCont’dRead:Write–2:1RandomAddressDRAMCommandSchedulePerformanceAnalyzeofSchedulePolicyCont’dRead:Write–2:1RandomAddressPart1--DRAMBasicKnowledgeDRAMDeviceArchitectureDRAMAccessFlowDRAMBasicCommandsDRAMCommandSchedulePageHit/MissPageOpen/ClosePolicyBankInterleaveCommandsRe-OrderDRAMControllerBasicDRAMControllerFunction&ArchitectureAddressMappinginDRAMControllerDRAMControllerBasicFunctionofDRAMControllerCorrectfunctionofDRAMInitializationRefreshTimingLimitsSchedulethe