算術(shù)邏輯單元英文演示文稿

算術(shù)邏輯單元英文演示文稿現(xiàn)在是1頁\一共有36頁\編輯于星期三（優(yōu)選）算術(shù)邏輯單元英文現(xiàn)在是2頁\一共有36頁\編輯于星期三5.1ThevonNeumanncomputermodelThevastmajorityofcomputersystemsusedtodayareconstructedonthevanNeumanncomputermodel.Acomputerisviewedasastoredprogramcomputer.Aprogramisasequenceofinstructions,eachofwhichperformsabasicoperation.Beforeexecution,theprogramisstoredinmemoryalongwithdatatobemanipulated.Whenexecuted,theinstructionsinitareretrievedfrommemory,oneafteranother,andbroughtintotheprocessingunit.Decodesinstruction,retrievedata,performoperation,storesresultinregisterormemory.現(xiàn)在是3頁\一共有36頁\編輯于星期三Typicallyconsistsof3functionalblocks:acentralprocessingunit(CPU),mainmemory,aninput/outputsystem(I/O).ControlunitregistersALUCPUMainmemoryInput/OutputExternalBusThebasicorganizationofastored-programcomputer5.1ThevonNeumanncomputermodelInternalBus

現(xiàn)在是4頁\一共有36頁\編輯于星期三5.2ParallelfastaddersAnarithmeticunit(ALU)istheheartoftheCPUTheALUusuallyhasabinaryadderTheperformanceoftheALUismainlydeterminedbyitsadder.Weneedtodesignafastaddertogetridoftheexcessivecarry-propagationtimeoftheripple-carryadder.現(xiàn)在是5頁\一共有36頁\編輯于星期三DesignoffulladderFulladderwiththecarrybitCn-1.FnandCnaregivenasbelow: Fn＝XnYnCn-1+XnYnCn-1 +XnYnCn-1+XnYnCn-1 Cn＝XnYnCn-1+XnYnCn-1 +XnYnCn-1+XnYnCn-15.2Parallelfastadders現(xiàn)在是6頁\一共有36頁\編輯于星期三DesignoffulladderLogicmaps:Fn＝XnYnCn-1+XnYnCn-1+XnYnCn-1+XnYnCn-1Cn＝XnYnCn-1+XnYnCn-1+XnYnCn-1+XnYnCn-1FormedbytwohalfaddersFn:addresultofXn、YnandCn-1Fn=XnYnCn-15.2Parallelfastadders現(xiàn)在是7頁\一共有36頁\編輯于星期三DesignoffulladderAnbitaddercanbeproducedbyconnectingnfulladdersCarryistransferredserially,andFiiscalculatedwhenCi-1iscoming.Timeconsumedisdeterminedbynumberofbits.Asimple4bitsserialfulladder5.2Parallelfastadders現(xiàn)在是8頁\一共有36頁\編輯于星期三DesignofafastadderHowtoimprovethespeedofadder?ChangethepathwayofonebyonecarrybitsCn＝XnYnCn-1+XnYnCn-1+XnYnCn-1+XnYnCn-1

＝(Xn+Yn)Cn-1+XnYnThecarryofthefulladderoftheCidependsontheCi-1Althoughnfulladdersworkinparallel,thecarrysignalsaregeneratedandpropagatedinsequential.Theworst-caseofcarrypropagationoccurswhenacarrysignalpropagatesfromC0toCnallthewayalongthecarrypropagationcircuit.5.2Parallelfastadders現(xiàn)在是9頁\一共有36頁\編輯于星期三Carrylook-ahead（超前進位）ItreducessignificantlythecarrycreationtimebygeneratingthecarrysignalsforallthebitsatoncedirectlyfromtheinputcarryC0ThenatureofcarrypropagationC1isgeneratedaslongasoneofthesetwoconditionsismeeting：(1)BothofX1，Y1are“1”；(2)EitherofX1，Y1is“1”，andC0is“1”。ThenC1canbeexpressed：C1=X1Y1+(X1+Y1)C05.2Parallelfastadders現(xiàn)在是10頁\一共有36頁\編輯于星期三ThenatureofcarrypropagationC2isgeneratedaslongasoneofthefollowingconditionsissatisfied：(1)BothofX2and

Y2are“1”；(2)EitherofX2andY2is“1”，andX1andY1are“1”；(3)EitherofX2andY2is“1”，andeitherofX1andY1is“1”，withC0is“1”ThenC2canbeexpressed：C2=X2Y2

+(X2+Y2)X1Y1

+(X2+Y2)(X1+Y1)C05.2Parallelfastadders現(xiàn)在是11頁\一共有36頁\編輯于星期三ThenatureofcarrypropagationSimilarly，C3andC4canbecalculated：C3=X3Y3

+(X3+Y3)X2Y2

+(X3+Y3)(X2+Y2)X1Y1

+(X3+Y3)(X2+Y2)(X1+Y1)C0C4=X4Y4

+(X4+Y4)X3Y3

+(X4+Y4)(X3+Y3)X2Y2

+(X4+Y4)(X3+Y3)(X2+Y2)X1Y1

+(X4+Y4)(X3+Y3)(X2+Y2)(X1+Y1)C05.2Parallelfastadders現(xiàn)在是12頁\一共有36頁\編輯于星期三ThenatureofcarrypropagationCarrypropagatefunctionPiandcarrygeneratefunctionGi：

Gi=Xi·Yi carrygeneratefunction Pi=Xi+Yi carrypropagatefunction

Gi：whenXiandYiare“1”，nomatterwhetherthereislow-ordercarrybit，thecurrentcarrybitisgenerated.Pi：wheneitherofXiandYiis1，ifthereexistlow-ordercarrybit,thenCi-1ispropagatedtohigh-ordercarrybit5.2Parallelfastadders現(xiàn)在是13頁\一共有36頁\編輯于星期三ThenatureofcarrypropagationPutP1,G1intoC1～C4：

C1=G1+P1C0 （low-orderbit）

C2=G2+P2G1+P2P1C0 C3=G3+P3G2+P3P2G1+P3P2P1C0 C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C05.2Parallelfastadders現(xiàn)在是14頁\一共有36頁\編輯于星期三ThenatureofcarrypropagationSincetheinputvariablestakeinvertedvalues,itsoutputgeneratestheinvertedvariables,“NAND”,“NOR”.“AND-OR-NOT”canbereadjustedas: Gi=Xi·Yi Gi=Xi·Yi=Xi+Yi carrygenerate Pi=Xi+Yi Pi=Xi+Yi=

Xi·Yi carrypropagate Gi·Pi=(Xi+Yi)·Xi·Yi=

Xi·Yi=Pi C1=G1+P1C0 C1=G1+P1C0=G1·P1C0=G1·(P1+C0)=G1·P1+G1·C0=P1+G1·C05.2Parallelfastadders現(xiàn)在是15頁\一共有36頁\編輯于星期三ThenatureofcarrypropagationC1=P1+G1C0 C2=P2+G2P1+G2G1C0 C3=P3+G3G2+G3G2P1+G3G2G1C0 C4=P4+G4P3+G4G3P2+G4G3G2P1+G4G3G2G1C05.2Parallelfastadders現(xiàn)在是16頁\一共有36頁\編輯于星期三5.2ParallelfastaddersThefour-bitcarrylook-aheadadder現(xiàn)在是17頁\一共有36頁\編輯于星期三5.2ParallelfastaddersTheblockcarrylook-aheadcircuitTheoreticallyspeaking,expressionC1~C4canbeexpandedtohigherorderbitsupton-1forn>4.However,asthebitnumberincreases,thenumberofproducttermsandmaximumnumberofliteralsinaproducttermintheexpressionwouldincreaseproportionally.Sowelimitthefan-inofanANDgateoranORgateto5.Themaximalallowablesizeofasingle-stagecarrylook-aheadcircuitis4bits.現(xiàn)在是18頁\一共有36頁\編輯于星期三5.2ParallelfastaddersTheblockcarrylook-aheadcircuit現(xiàn)在是19頁\一共有36頁\編輯于星期三5.2ParallelfastaddersTheblockcarrylook-aheadcircuit G’=G3+P3G2+P3P2G1+P3P2P1G0 P’=P3P2P1P074182

G3P3G2P2G1P1G0P0

G’P’C3C2C1C0現(xiàn)在是20頁\一共有36頁\編輯于星期三Theresultofcarrygeneratefunctionof74181Gis“1”aslongasoneoftheseconditionssatisfied：(1)BothofX3andY3are“1”，thatisG3=1；(2)EitherofX3andY3is“1”，andX2andY2areall“1”，thatisP3G2=1(3)EitherofX3andY3is“1”，andoneofX2andY2is“1”，andbothofX1andY1are“1”，thatisP3P2G1=1；(4)OneofX3andY3is“1”，andoneofX2andY2is“1”，andoneofX1andY1is“1”，andbothX0andY0are“1”，thatisP3P2P1G0=1。Therefore：

G=G3+P3G2+P3P2G1+P3P2P1G05.2Parallelfastadders現(xiàn)在是21頁\一共有36頁\編輯于星期三Therequirementstomeetgroupcarrypropagatefunctionof74181Pequals1is：EitherX3orY3is“1”，EitherX2orY2is“1”，EitherX1orY1is“1”，EitherX0orY0is“1”。Therefore：

P=P3P2P1P05.2Parallelfastadders現(xiàn)在是22頁\一共有36頁\編輯于星期三LetCn1,Cn2,Cn3(C3,C7,C11)bethecarrysofchip0tochip1,chip1tochip2andchip2tochip3.ReplaceG1,G2andG3byGN0,GN1,GN2.ReplaceP1,P2,P3byPN0,PN1,PN2.ReplaceC0byCn.ThenCn+x,Cn+y,Cn+ycanbegainedasfollows:

5.2Parallelfastadders現(xiàn)在是23頁\一共有36頁\編輯于星期三Theblockcarrylook-aheadcircuit16-bitfastaddersadderA15~A12B15~B1274182adderA11~A8B11~B8adderA7~A4B7~B4adderA3~A0B3~B0C0F3~F0G4P4C3G3P3C2G2P2C1G1P1F7~F4F11~F8F15~F12GPC05.2Parallelfastadders現(xiàn)在是24頁\一共有36頁\編輯于星期三5.3AnalysisofthedesignofacommercialALUchipALUcanimplementbasicarithmeticoperationsandlogicaloperations.Thissectionanalyzethedesignprocessofthecommercial4-bitsALUchipSN74181.現(xiàn)在是25頁\一共有36頁\編輯于星期三SN74181Logicmapsandfunctiontableof4-bitsALUS3S2S1S0PositivelogicM=HLogicopM=LarithmeticoperationCn=1Cn=0LLLLAAAadd1LLLHA+BA+B(A+B)add1LLHLA·BA+B(A+B)add1LLHH“0”Sub1“0”LHLLA·BAadd(A·B)Aadd(A·B)add1LHLHB(A·B)add(A+B)(A·B)add(A+B)add1LHHLABAsubBsub1AsubBLHHHA·B(A·B)sub1A·?5.3AnalysisofthedesignofacommercialALUchip現(xiàn)在是26頁\一共有36頁\編輯于星期三SN74181S3S2S1S0PositivelogicM=HLogicopM=LarithmeticoperationCn=1Cn=0HLLLA+BAadd(A·B)Aadd(A·B)add1HLLHABAaddBAaddBadd1HLHLB(A·B)add(A+B)(A·B)add(A+B)add1HLHHA·B(A·B)sub1A·BHHLL“1”AaddAAaddAadd1HHLHA+BAadd(A+B)Aadd(A+B)add1HHHLA+BAadd(A+B)Aadd(A+B)add

1HHHHAAsub1A?5.3AnalysisofthedesignofacommercialALUchipLogicmapsandfunctiontableof4-bitsALU現(xiàn)在是27頁\一共有36頁\編輯于星期三1111000000000000000000G0=A0+B0=A0B0

P0=A0B0=A0+B0G0⊕P0=G0P0+G0P0

=(A0+B0)(A0+B0)

+(A0B0)(A0B0)=0+A0B0+A0B0+0+0=A0⊕B0現(xiàn)在是28頁\一共有36頁\編輯于星期三00000000A0B0C0??A1B1C1??現(xiàn)在是29頁\一共有36頁\編輯于星期三SN74181Pinsof741815.3AnalysisofthedesignofacommercialALUchip現(xiàn)在是30頁\一共有36頁\編輯于星期三16-bitsALUFour74181circuitscanforms16-bitsALUFastcarryinchip,andonebyonebetweenchips.SoitwouldtakerelativelongtimetogenerateF0～F1516-bitsALUformedby4ALUchips5.3AnalysisofthedesignofacommercialALUchip現(xiàn)在是31頁\一共有36頁\編輯于星期三5.3AnalysisofthedesignofacommercialALUchip16-bitsALUTake4bitsasagroup.Usingmethodlike“4-bitcarrylook-aheadadder”toimplement16-bitsALU(formedby4ALUchips)，a16-bitfastALUcanbegained.74181

ALUcangenerateGn，Pn，then16-bitfastALUcanbeimplementedbyANDORNOTgatesand4ALUchips74182(Look-aheadcarryextender)canbegainedbyimplementinglogiccircuitofCn1、Cn2、Cn3現(xiàn)在是32頁\一共有36頁\編輯于星期三16-bitsfastALU16-bitfastALU74181A15~A12B15~B127418274181A11~A8B11~B874181A7~A4B7~B474181A3~A0B3~B0C0F3~F0G4P4C3G3P3C2G2P2C1G1P1F7~F4F11~F8F15~F12GPC05.3AnalysisofthedesignofacommercialALUchip現(xiàn)在是33頁\一共有36頁\編輯于星期三32-bitsfastALUTwo16-bit74182andeigh