分析教案講稿fdcp

Primitive:DFlip-FlopwithNegative-EdgeClockandAsynchronousPresetandClearCCD

Q

FDCP_1isasingleD-typeflip-flopwithdata(D),asynchronouspreset(PRE)andclear(CLR)inputs,anddataoutput(Q).TheasynchronousPRE,whenHigh,setsthe(Q)outputHigh;CLR,whenHigh,resetstheoutputLow.Dataonthe(D)inputisloadedintotheflip-flopwhenPREandCLRareLowontheHigh-to-Lowclock(C)Theflip-flopisasynchronouslycleared,outputLow,whenpowerisForSpartan-3Edevices,power-onconditionsaresimulatedwhenglobalset/reset(GSR)isactive.GSRdefaultstoactive-HighbutcanbeinvertedbyaddinganinverterinfrontoftheGSRinputoftheSpartan-3Esymbol.DCQ1XXX001XX100000011Thisdesignelementtypicallyisinferredinthedesigncode;however,theelementcanbeinstantiatedforcaseswherestrictcementcontrol,relativecementcontrol,orinitializationattributesmustbeapplied.Allowed 0,0SetstheinitialvalueofQoutputafterconfigurationForMoreConsulttheSpartan-3EDataSpartan-3ELibrariesGuideforSchematic ISE Spartan-3ELibrariesGuideforSchematicDesignsISE原語：具有下降沿時(shí)鐘以及異步預(yù)設(shè)和清除PRE的D觸發(fā)器FDCP_1是一個(gè)單D型觸發(fā)器，具有數(shù)據(jù)(D)、異步預(yù)設(shè)(PRE)和清除(CLR)輸入以及數(shù)據(jù)輸出(Q)）。異步PRE當(dāng)為，將Q)輸出設(shè)置為CLR當(dāng)時(shí)，將輸出復(fù)位為低電平。(D)輸入上的數(shù)據(jù)PRECLR(C)Q轉(zhuǎn)換時(shí)為低電平時(shí)，D加載到觸發(fā)器中。CLRSpartan-3E器件，全局設(shè)置/X8357GSR)處于活動(dòng)狀態(tài)。GSR默認(rèn)為有效，但可以通過在Spartan-3E符號(hào)的GSR輸入前面添加反相器來反轉(zhuǎn)。輸入輸出CLRPREDCQ1.XXX01XX000↓001↓INIT0,10GSRQ輸出的初始值有關(guān)詳細(xì)信息，請(qǐng)參閱Spart