EDA技術數(shù)字時鐘實驗報告

JIUJIANGUNIVERSITYEDA技術實驗報告實驗名稱：數(shù)字時鐘院（系）：電子工程學院班級：B1111學號：52號實驗室：實驗樓307專業(yè)：電子信息工程技術姓名：高芬日期：2012年12月15日實驗目的設計一個可以計時的數(shù)字時鐘，其顯示時間范圍是00:00:00~23:59:59，且該時鐘具有暫停計時、清零等功能。實驗器材1、SOPC實驗箱2、計算機（裝有QuartusII7.0軟件）實驗預習1、了解時鐘設計原理和各主要模塊的設計方法。2、提前預習，編寫好主模塊的VHDL程序。實驗原理一個完整的時鐘應由4部分組成：秒脈沖發(fā)生電路、計數(shù)部分、譯碼顯示部分（和時鐘調(diào)整部分）。1、秒脈沖發(fā)生：可以設計分頻電路對系統(tǒng)時鐘50MHz進行50000000分頻從而得到穩(wěn)定的1Hz基準信號。2、計數(shù)部分：應設計1個60進制秒計數(shù)器、1個60進制分計數(shù)器、1個24進制時計數(shù)器用于計時。秒計數(shù)器應定義clk（時鐘輸入）、rst（復位）兩個輸入引腳，Q3~Q0（秒位）、Q7~Q4（十秒位）、Co（進位位）9個輸出引腳。分、時計數(shù)器類似。3、譯碼顯示部分：在時鐘信號的控制下輪流選擇對十時、時、十分、分、十秒、秒輸入信號進行譯碼輸出至XQ7~XQ0，并通過DIG0~DIG5輸出相應的選通信號選擇數(shù)碼管。每位顯示時間控制在1ms左右。時鐘信號可由分頻電路引出。源程序如下所示：頂層文件（count_time.vhd）程序及波形圖：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYcount_timeISPORT(clk,rst:INSTD_LOGIC;co:OUTSTD_LOGIC;dig1:OUTSTD_LOGIC_VECTOR(5DOWNTO0);seg1:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDcount_time;ARCHITECTUREoneOFcount_timeISCOMPONENTfenpinISPORT(clk11,clk12,rst11,rst12:INSTD_LOGIC;cok1,cok2:OUTSTD_LOGIC);ENDCOMPONENT;COMPONENTscan_ledISPORT(clk2:INSTD_LOGIC;doe:INSTD_LOGIC_VECTOR(23DOWNTO0);dig2:OUTSTD_LOGIC_VECTOR(5DOWNTO0);seg2:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCOMPONENT;COMPONENTcountISPORT(clk3,rst2:INSTD_LOGIC;cox:OUTSTD_LOGIC;m:OUTSTD_LOGIC_VECTOR(23DOWNTO0));ENDCOMPONENT;SIGNALa:STD_LOGIC_VECTOR(23DOWNTO0);SIGNALb:STD_LOGIC;SIGNALc:STD_LOGIC;BEGINu1:fenpinPORTMAP(clk11=>clk,clk12=>clk,rst11=>rst,rst12=>rst,cok1=>b,cok2=>c);u2:scan_ledPORTMAP(clk2=>c,doe=>a,dig2=>dig1,seg2=>seg1);u3:countPORTMAP(clk3=>b,rst2=>rst,cox=>co,m=>a);ENDARCHITECTUREone;2.分頻部分(fenpin.vhd)程序及波形圖：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_Unsigned.ALL;ENTITYfenpinISPORT(clk11,clk12,rst11,rst12:INSTD_LOGIC; cok1,cok2:OUTSTD_LOGIC);END;ARCHITECTUREoneOFfenpinISsignalq1:INTEGERRANGE49999999DOWNTO0;signalq2:INTEGERRANGE99999DOWNTO0;signalc1,c2:STD_LOGIC;BEGINPROCESS(clk11,rst11,q1,c1)BEGINIFrst11='1'THENq1<=0;ELSIFclk11'EVENTANDclk11='1'THENIFq1<49999999THENq1<=q1+1;c1<='0';ELSEq1<=0;c1<=NOTc1;ENDIF;ENDIF;ENDPROCESS;cok1<=c1;PROCESS(clk12,rst12,q2,c2)BEGINIFrst12='1'THENq2<=0;ELSIFclk12'EVENTANDclk12='1'THENIFq2<99999THENq2<=q2+1;c2<='0';ELSEq2<=0;c2<=notc2;ENDIF;ENDIF;ENDPROCESS;cok2<=c2;END;計數(shù)部分（count.vhd)程序及波形圖：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYcountISPORT(clk3,rst2:INSTD_LOGIC;cox:OUTSTD_LOGIC;m:OUTSTD_LOGIC_VECTOR(23DOWNTO0));ENDcount;ARCHITECTUREoneOFcountISSIGNALq1,q2,q3,q4,q5,q6:STD_LOGIC_VECTOR(3DOWNTO0):="0000";SIGNALcq1,co1,cq2,co2,cq3,co3:STD_LOGIC;BEGINPROCESS(clk3,rst2)BEGINIFrst2='1'THENq1<="0000";cq1<='0';ELSIFclk3'EVENTANDclk3='1'THENIFq1<9THENq1<=q1+1;cq1<='0';ELSEq1<="0000";cq1<='1';ENDIF;ENDIF;ENDPROCESS;PROCESS(cq1,rst2)beginIFrst2='1'THENq2<="0000";co1<='0';ELSIFcq1'EVENTANDcq1='1'THENIFq2<5THENq2<=q2+1;co1<='0';ELSEq2<="0000";co1<='1';ENDIF;ENDIF;ENDPROCESS;PROCESS(co1,rst2)BEGINIFrst2='1'THENq3<="0000";cq2<='0';ELSIFco1'EVENTANDco1='1'THENIFq3<9THENq3<=q3+1;cq2<='0';ELSEq3<="0000";cq2<='1';ENDIF;ENDIF;ENDPROCESS;PROCESS(cq2,rst2)beginIFrst2='1'THENq4<="0000";co2<='0';ELSIFcq2'EVENTANDcq2='1'THENIFq4<5THENq4<=q4+1;co2<='0';ELSEq4<="0000";co2<='1';ENDIF;ENDIF;ENDPROCESS;PROCESS(co2,rst2)BEGINIFrst2='1'THENq5<="0000";cq3<='0';ELSIFco2'EVENTANDco2='1'THENIFq6=2THENIFq5<3THENq5<=q5+1;cq3<='0';ELSEq5<="0000";cq3<='1';ENDIF;ELSEIFq5<9THENq5<=q5+1;cq3<='0';ELSEq5<="0000";cq3<='1';ENDIF;ENDIF;ENDIF;endprocess;PROCESS(cq3,rst2)BEGINIFrst2='1'THENq6<="0000";co3<='0';ELSIFcq3'eventandcq3='1'THENIFq6<2THENq6<=q6+1;co3<='0';ELSEq6<="0000";co3<='1';ENDIF;ENDIF;ENDPROCESS;m<=q6&q5&q4&q3&q2&q1;cox<=NOT(cq1XORco1XORcq2XORco2XORcq3XORco3);ENDARCHITECTURE;顯示部分（scan_led.vhd)程序及波形圖：LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;ENTITYscan_ledISPORT(clk2:INSTD_LOGIC;doe:INSTD_LOGIC_VECTOR(23DOWNTO0);dig2:OUTSTD_LOGIC_VECTOR(5DOWNTO0);seg2:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDscan_led;ARCHITECTUREexampleOFscan_ledISSIGNALa:STD_LOGIC_VECTOR(2DOWNTO0):="000";SIGNALb:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(clk2)BEGINIFclk2'eventandclk2='1'THENIFa="101"THENa<="000";ELSEa<=a+1;ENDIF;ENDIF;ENDPROCESS;PROCESS(a)BEGINCASEaISWHEN"101"=>b<=doe(3DOWNTO0);dig2<="111110";WHEN"100"=>b<=doe(7DOWNTO4);dig2<="111101";WHEN"011"=>b<=doe(11DOWNTO8);dig2<="111011";WHEN"010"=>b<=doe(15DOWNTO12);dig2<="110111";WHEN"001"=>b<=doe(19DOWNTO16);dig2<="101111";WHEN"000"=>b<=doe(23DOWNTO20);dig2<="011111";WHENOTHERS=>NULL;ENDCASE;ENDPROCESS;PROCESS(b)BEGINCASEbISWHEN"0000"=>seg2<="11000000";WHEN"0001"=>seg2<="11111001";WHEN"0010"=>seg2<="10100100";WHEN