FPGA課程設(shè)計(jì)基于RAM的十口8位計(jì)數(shù)器

FPGA課程設(shè)計(jì)基于RAM的十口8位計(jì)數(shù)器FPGARAM8數(shù)器v>FPGA課程設(shè)計(jì)報(bào)告題目：RAM8通信與信息工程學(xué)院專業(yè)班級(jí)：導(dǎo)師姓名：起止時(shí)間：2012-9-10至2012-9-21年月日FPGA課程設(shè)計(jì)報(bào)告提綱1．任務(wù)用一個(gè)10×8RAM1081~10，1MHz，1Hz。FPGA（led）作為選擇計(jì)數(shù)器的計(jì)數(shù)值輸出。2．RAMFPGA3．使用環(huán)境(軟件/境，設(shè)備等)前仿modelsim6.1f后仿QuartusII10.14．FPGARAM8RAMRAM10×8RAM1~104.系統(tǒng)工作流程：切換端口讀出數(shù)據(jù)開始計(jì)數(shù)暫停計(jì)數(shù)存入數(shù)據(jù)計(jì)數(shù)流程5．切換端口讀出數(shù)七段顯示譯碼器譯碼輸出到數(shù)碼管顯示讀取結(jié)果輸出流程6．分頻：1Hz的秒計(jì)時(shí)頻率，用來進(jìn)行秒計(jì)時(shí)；4.2設(shè)計(jì)方案信號(hào)定義：分頻模塊Clk_50MHzclk_1Hzresetclk_1MHz分頻：1Hzclk_50MHz；分頻信號(hào)clk_1Hz；分頻信號(hào)clk_1MHz；計(jì)數(shù)模塊由RAM讀出初值doutclkclk_1hzdout[7:0]din[7:0]startstartreset切換端口讀出數(shù)據(jù)開始計(jì)數(shù)暫停計(jì)數(shù)存入數(shù)據(jù)計(jì)數(shù)：開始計(jì)數(shù)start計(jì)數(shù)器復(fù)位reset；計(jì)數(shù)輸出din[7:0]；計(jì)數(shù)置數(shù)add；七段顯示譯碼器數(shù)碼管dout顯示模塊wr[7:0]dinclk_50MHz10×8RAM計(jì)數(shù)器dout[7:0][3:0]wr_addressrd[3:0]rd_adddressreseteetetstartaddRAM：10×8的RAM存儲(chǔ)陣列10個(gè)字每個(gè)子8位輸入端輸入地址wr_address[3:0]；輸入數(shù)據(jù)din[7:0]；上升沿有效寫入信號(hào)wr；rd_address[3:0]；輸出數(shù)據(jù)dout[7:0]；上升沿有效讀信號(hào)rd；端口I/O功能rdI讀使能，高電平有效；dinramwrO效；ramdout.Wr_address[3:0]I寫地址din[7:0]I數(shù)據(jù)輸入口，內(nèi)部接口dout[7:0]O數(shù)據(jù)輸出，內(nèi)部數(shù)據(jù)傳送resetI端，時(shí)鐘下降沿有效addI計(jì)數(shù)器置數(shù)端startI開始/暫停鍵,高電平開始，低電平暫停Rd_address[3:0]I讀地址rd_clkI讀時(shí)鐘，下降沿觸發(fā)wr_clkI寫時(shí)鐘，上升沿觸發(fā)地址劃分：ain[3:0]Ram存儲(chǔ)單元00010000_000100100000_001000110000_001101000000_010001010000_010101100000_011001110000_011110000000_100010010000_100110100000_1010En數(shù)碼管（led）顯示模塊startRAM/輸出1~10clk_1hzclk計(jì)數(shù)模塊置數(shù)控制分頻模塊控制模塊：開始、暫停、返回初值，計(jì)數(shù)器顯示切換4.3功能驗(yàn)證方案（1）RAM用軟件工具對其功能進(jìn)行驗(yàn)證。雙端口RAM計(jì)數(shù)器功能和指標(biāo)的詳細(xì)描述請參見《雙端口RAM計(jì)數(shù)器技術(shù)規(guī)范.docRAM要在硬件驗(yàn)證和測試過程中完成。在本驗(yàn)證過程中將驗(yàn)證以下內(nèi)容：（2）驗(yàn)證環(huán)境及工具根據(jù)情況驗(yàn)證過程將使用以下的環(huán)境和工具進(jìn)行：a)windows環(huán)境下使用ModelSim仿真工具；b)windows環(huán)境下使用QuartusII工具。為進(jìn)行驗(yàn)證還應(yīng)當(dāng)建立仿真激勵(lì)模塊（3）預(yù)確認(rèn)a.系統(tǒng)主要技術(shù)參數(shù)；經(jīng)分析，系統(tǒng)的的主要參數(shù)包括：引腳數(shù)目，引腳工作電壓，電源電壓，系統(tǒng)的工作頻率。b.系統(tǒng)的模塊數(shù)目及各模塊實(shí)現(xiàn)的功能及如何知道模塊工作正常；c.總模塊驗(yàn)證，看總系統(tǒng)是否正常工作。(4)仿真確認(rèn)：a.目的初步確認(rèn)系統(tǒng)是否完成預(yù)期設(shè)計(jì)的功能；RAMclk(50M)enclk_1Hz顯示模塊led50MHz1Hz.1Hz②計(jì)數(shù)模塊：編寫完成后可通過查看仿真圖形確認(rèn)計(jì)數(shù)范圍，位寬等功能的正確。③RAMRAMRAM④顯示模塊：把計(jì)數(shù)的結(jié)果通過七段顯示譯碼器顯示在數(shù)碼管上，觀察數(shù)碼管上的數(shù)字變化規(guī)律即可驗(yàn)證顯示模塊是否正確。驗(yàn)證空標(biāo)志產(chǎn)生邏輯：先將復(fù)位信號(hào)置0(有效)，在一定時(shí)間內(nèi)看系統(tǒng)是否產(chǎn)生空標(biāo)志；驗(yàn)證正常情況下的信號(hào)：1（即復(fù)位無效），與想要得到的信號(hào)進(jìn)行比較。4.4moduleFPQ(clk_50MHz,clk_1MHz,reset,clk_1Hz);inputclk_50MHz,reset;outputclk_1MHz,clk_1Hz；regclk_1Hz=0;regclk_1MHz=0;reg[31:0]cnt1=32＇d0;reg[31:0]cnt2=32＇d0;always@(posedgeclk_50MHzornegedgereset)beginif(!reset)clk_1Hz<=32＇d0;elsebeginif(cnt1==32＇d100)begincnt1<=32＇d0;clk_1Hz<=~clk_1Hz;endelsecnt1<=cnt1+32＇d1;endendalways@(posedgeclk_50MHzornegedgereset)beginif(!reset)clk_1MHz<=32＇d0;elsebeginif(cnt2==32＇d255)begincnt2<=32＇d0;clk_1MHz<=~clk_1MHz;endelsecnt2<=cnt2+32＇d1;endendendmodule分頻器模塊激勵(lì)：moduleFPQ_test;regclk_50MHz,reset;wireclk_1MHz;wireclk_1Hz;always#2clk_50MHz=~clk_50MHz;FPQfpq(.reset(reset),.clk_50MHz(clk_50MHz),.clk_1MHz(clk_1MHz),.clk_1Hz(clk_1Hz));initialbeginreset<=0;clk_50MHz<=0;#100reset<=1;endendmodule計(jì)數(shù)器模塊：moduleJSQ(start,data,clk_1Hz,add,c_out);inputclk_1Hz,add;inputstart;input[7:0]data;outputc_out;reg[7:0]c_out;always@(posedgeclk_1Hzornegedgeadd)beginif(!add)beginc_out<=data;endelsebeginif(start)beginc_out<=c_out+8＇d1;if(c_out==8＇d255)beginc_out<=0;endelsec_out<=c_out+8＇d1;endelsec_out<=c_out;endendendmodule計(jì)數(shù)器激勵(lì)：moduleJSQ_test;regstart,add;regclk_1Hz;reg[7:0]data;wire[7:0]c_out;always#1clk_1Hz=~clk_1Hz;JSQjsq(.start(start),.add(add),.clk_1Hz(clk_1Hz),.data(data),.c_out(c_out));initialbeginclk_1Hz=0;add=0;start=0;data=8＇d1;#15add=1;#15start=1;#600start=0;endendmodule數(shù)碼管顯示模塊：moduleSMG(clk_1MHz,data,data_g,data_s,data_b);input[7:0]inputclk_1MHz；outputdata_b;outputdata_s;outputdata_g;reg[6:0]data_b;reg[6:0]data_s;reg[6:0]data_g;reg[7:0]mid_b;reg[7:0]mid_s;reg[7:0]mid_g;always@(posedgeclk_1MHz)beginmid_b<=data/100;mid_s<=data%100/10;mid_g<=data%10;endalways@(mid_b)begincase(mid_b)7＇d0:data_b<=7＇hC0;7＇d1:data_b<=7＇hF9;7＇d2:data_b<=7＇hA4;7＇d3:data_b<=7＇hB0;7＇d4:data_b<=7＇h99;7＇d5:data_b<=7＇h92;7＇d6:data_b<=7＇h82;7＇d7:data_b<=7＇hf8;7＇d8:data_b<=7＇h80;7＇d9:data_b<=7＇h90;default:data_b<=7＇hC0;endcaseendalways@(mid_s)begincase(mid_s)7＇d0:data_s<=7＇hC0;7＇d1:data_s<=7＇hF9;7＇d2:data_s<=7＇hA4;7＇d3:data_s<=7＇hB0;d4:data_s<=7＇h99;7＇d5:data_s<=7＇h92;7＇d6:data_s<=7＇h82;7＇d7:data_s<=7＇hf8;7＇d8:data_s<=7＇h80;7＇d9:data_s<=7＇h90;default:data_s<=7＇hC0;endcaseendalways@(mid_g)begincase(mid_g)7＇d0:data_g<=7＇hC0;7＇d1:data_g<=7＇hF9;7＇d2:data_g<=7＇hA4;d3:data_g<=7＇hB0;7＇d4:data_g<=7＇h99;7＇d5:data_g<=7＇h92;7＇d6:data_g<=7＇h82;7＇d7:data_g<=7＇hf8;7＇d8:data_g<=7＇h80;7＇d9:data_g<=7＇h90;default:data_g<=7＇hC0;endcaseendendmodule管顯示模塊激勵(lì)：moduleSMG_test;reg[7:0]data;regclk_1MHz;wire[6:0]data_g;wire[6:0]data_s;wire[6:0]data_b;SMGsmg(.data(data),.clk_1MHz(clk_1MHz),.data_g(data_g),.data_s(data_s),.data_b(data_b));always#10clk_1MHz=~clk_1MHz;initialbegindata=0;clk_1MHz=0;#25data=35;#25data=15;#25data=93endendmoduleRAMmoduleRAM(reset,wr,wr_clk,wr_address,din,rd,rd_clk,rd_address,dout);inputwr,wr_clk,reset;input[3:0]wr_address;input[7:0]din;inputrd,rd_clk;input[3:0]rd_address;output[7:0]dout;reg[7:0]dout=0;reg[7:0]mem[1:10];always@(posedgewr_clkornegedgereset)beginif(!reset)beginmem[1]<=8＇d1;mem[2]<=8＇d2;mem[3]<=8＇d3;mem[4]<=8＇d4;mem[5]<=8＇d5;mem[6]<=8＇d6;mem[7]<=8＇d7;mem[8]<=8＇d8;mem[9]<=8＇d9;mem[10]<=8＇d10;endelsebeginif(wr)beginif(wr_address<=4＇d10)mem[wr_address]<=din;endendendalways@(posedgerd_clkornegedgereset)beginif(!reset)dout<=8＇d0;elsebeginif(rd)begindout<=mem[rd_address];endendendendmoduleRAM模塊激勵(lì)：moduleRAM_test;regreset,wr,rd;regwr_clk,rd_clk;reg[3:0]wr_address,rd_address;reg[7:0]din;wire[7:0]mem[1:10];wire[7:0]dout;RAMram(.reset(reset),.wrn(wr),.wr_clk(wr_clk),.wr_address(wr_address),.rd(rd),.rd_clk(rd_clk),.rd_address(rd_address),.din(din),.dout(dout));always#1wr_clk=~wr_clk;always#1rd_clk=~rd_clk;initialbeginwr_clk<=0;rd_clk<=0;reset=0;wr<=0;rd<=0;wr_address<=4＇d0;rd_address<=4＇d0;din<=8＇d0;#15reset<=1#15rd<=1;#25rd_address<=4＇d4;wr<=1;#35din<=8＇d5;wr_address<=4＇d1;rd_address<=4＇d1;#15din<=8＇d8;wr_address<=4＇d6;rd_address<=4＇d6;#15reset<=0;rd_address<=4＇d4;endendmodule頂層模塊：moduleRAM_count(reset,add,start,clk_50MHz,wr,wr_address,din,rd,rd_address,data_g,data_s,data_b);inputreset,add,start,wr,rd,clk_50MHz;input[3:0]wr_address,rd_address;input[7:0]din;output[6:0]data_g,data_s,data_b;wire[6:0]data_g,data_s,data_b;wire[7:0]dout;wire[7:0]mid_data;wiremid_clk_1Hz;wiremid_clk_1MHz;FPQfpq(.reset(reset),.clk_50MHz(clk_50MHz),.clk_1MHz(mid_clk_1MHz),.clk_1Hz(mid_clk_1Hz));RAMram(.reset(reset),.wr(wr),.wr_clk(mid_clk_1MHz),.wr_address(wr_address),.din(din),.rd(rd),.rd_clk(mid_clk_1MHz),.rd_address(rd_address),.dout(mid_data));JSQjsq(.add(add),.data(mid_data),.clk_1Hz(mid_clk_1Hz),.start(start),.c_out(dout));SMGsmg(.clk_1MHz(mid_clk_1Hz),.data(dout),.data_g(data_g),.data_s(data_s),.data_b(data_b));Endmodule頂層模塊激勵(lì)：moduleRAM_count_test;regreset,add,start,wr,rd;regclk_50MHz;reg[3:0]wr_address,rd_address;reg[7:0]din;wire[6:0]data_g,data_s,data_b;RAM_countram(.reset(reset),.add(add),.start(start),.wr(wr),.rd(rd),.clk_50MHz(clk_50MHz),.wr_address(wr_address),.rd_address(rd_address),.din(din),.data_g(data_g),.data_s(data_s),.data_b(data_b));always#1clk_50MHz=~clk_50MHz;initialbeginreset=1;start=1;din=1;wr=0;rd=1;wr_address=4＇d1;rd_address=4＇d1;clk_50MHz=0;add=1;#125reset=0;#250reset=1;#250add=0;#250add=1;#250wr=0;rd=1;#10000start=0;#250wr=1;rd=0;endendmodule4.5綜合及布局布線報(bào)告和引腳分布報(bào)告綜合圖