數(shù)電英文版全冊(cè)配套課件

《數(shù)電(英文版）》全冊(cè)配套課件2DigitalLogicDesignandApplication

ChenYan

Lecture#1IntroductionUESTC,Spring20113InstructorChenYanOffice:研究院大樓508

航空航天學(xué)院SchoolofAstronautics&AeronauticsEMAIL:blastchen@4ResourcesTextbook:DIGITALDESIGN–Principles&Practices,(FourthEdition),JohnF.Wakerly,HigherEducationPress,2007

References:數(shù)字邏輯設(shè)計(jì)及應(yīng)用，姜書艷主編，清華大學(xué)出版社，2007數(shù)字電子技術(shù)基礎(chǔ)（第5版），閻石主編，高等教育出版社，2007數(shù)字設(shè)計(jì)——原理與實(shí)踐（第4版），JohnF.Wakerly,林生等譯,機(jī)械工業(yè)出版社，20075ResourcesCourseWebpage95/wlxt/index.aspx電子科技大學(xué)/互動(dòng)教學(xué)空間/網(wǎng)絡(luò)學(xué)堂/自動(dòng)化工程學(xué)院/數(shù)字邏輯設(shè)計(jì)及應(yīng)用[姜書艷]/教學(xué)錄像

部分習(xí)題解答/programs.univXilinx的大學(xué)計(jì)劃，提供了大量的產(chǎn)品資料、課程資料以及用于數(shù)字設(shè)計(jì)實(shí)驗(yàn)課程的芯片和插件Prerequisites《電路分析基礎(chǔ)》《模擬電路基礎(chǔ)》AboutthenameOthernamesAssociationbetweenDigital&LogicalJin.UESTC.6Whatdoesdigitaltech.do?7電視技術(shù)雷達(dá)技術(shù)通信技術(shù)計(jì)算機(jī)、自動(dòng)控制航空航天數(shù)碼相機(jī)MP3、MP4人類社會(huì)進(jìn)入信息數(shù)字化的時(shí)代，“數(shù)字邏輯”是數(shù)字技術(shù)的基礎(chǔ)，是電子信息類各專業(yè)的主要技術(shù)基礎(chǔ)課程之一?！癲igitalize”：許多傳統(tǒng)使用模擬技術(shù)的領(lǐng)域轉(zhuǎn)而使用數(shù)字技術(shù)。8TopicstobeCoveredIntroduction,NumberSystemsandCodes: 1?weeksLogicsignalsandGates,CMOSLogic:1?weeksCombinationalLogicDesignPrinciples:2-3weeksSwitchingAlgebra,Combinational-CircuitAnalysisandSynthesisCombinationalLogicDesignPractices:3weeksDecoders,Encoders,Multiplexers,Comparators,etc.

HardwareDescriptionLanguages:1weekSequentialLogicDesignPrinciples:2-3weeksLatches,Flip-Flops,ClockedSynchronousState-MachineAnalysisandDesignSequentialLogicDesignPractices: 3weeksSSILatchesandFlip-Flops,Counters,ShiftRegisters,Iterative,…Other:Memory,CPLDSandFPGAS,A/D,D/ACircuits:1weeks一、concepts&fundamentals二、集成電路為主；邏輯功能為主三、重視實(shí)踐本課程的重點(diǎn)是數(shù)字電路的基本概念、基本原理、分析方法、設(shè)計(jì)方法和實(shí)驗(yàn)調(diào)試方法。只要掌握了基本的原理和方法，我們就可以分析給出的任何一種數(shù)字電路；也可以根據(jù)提出的任何一種邏輯功能，設(shè)計(jì)出相應(yīng)的邏輯電路。對(duì)于各類數(shù)字集成電路器件，重點(diǎn)是掌握他們的外部特性，包括邏輯功能和輸入、輸出端的電氣特性。為了更好的理解和運(yùn)用電路器件的外部特性，需要理解他們的輸入電路和輸出電路的結(jié)構(gòu)及其原理。至于內(nèi)部的電路結(jié)構(gòu)和詳細(xì)工作過(guò)程都不是重點(diǎn)，不需要去記憶。通過(guò)實(shí)驗(yàn)的訓(xùn)練，加深對(duì)理論知識(shí)的理解和掌握，同時(shí)更重要的是要學(xué)習(xí)和掌握電子技術(shù)實(shí)驗(yàn)的研究方法。將理論和實(shí)際有機(jī)地結(jié)合，學(xué)會(huì)用實(shí)驗(yàn)的方法分析和解決實(shí)際問(wèn)題。Conceptsofteaching&learning10GradesHomeworksandQuizzesinclass—15%ProjectsandPaper—15%MidtermExam—30%FinalExam—40%11Chapter1IntroductionWelcometotheworldofdigitaldesign.DigitalLogicDesignandApplication12Chapter1Introduction1.1AboutDigitalDesignAboutPrinciplesandPracticesImportantThemesinDigitalDesign…(P2)*131.2Analogvs.DigitalAnalog:1.2Analogvs.DigitalJin.UESTC.14Primaryparameters:frequency,bandwidth、powerBasicdevice：transistorsworkingatamplifyarea.Analog:valuesvaryoverabroadrangecontinuouslytvrectangularwave1forHigh；0forLow010011010特點(diǎn)：數(shù)值的大小和每次的增減都是量化單位的整數(shù)倍。Presentedasbinarycodesystem1.2Analogvs.Digital1.2Analogvs.DigitalTheproblemforanalogsignal…Theadvantagesofdigitalsignal…16signaldegradationamplification

模擬信號(hào)在傳輸過(guò)程中失真數(shù)字信號(hào)仍然可以保持

0、1抗干擾性強(qiáng);便于存儲(chǔ);便于分析和設(shè)計(jì)；便于利用計(jì)算機(jī)、DSP等進(jìn)行信號(hào)處理.電路中的電子器件工作在開關(guān)狀態(tài)，易于實(shí)現(xiàn)，便于集成化缺點(diǎn)：其表現(xiàn)形式的多樣化決定了對(duì)其的處理也是復(fù)雜多樣的。171.2Analogvs.DigitalDigitalsystemAnyinputsandoutputscanonlybe1or0!181.3DigitalDevicesGates（門）—themostbasicdigitaldevicesFlip-Flops（觸發(fā)器）—adevicethatstoreseithera0or1CombinationalCircuits（組合電路）SequentialCircuits（時(shí)序電路）ANDgateORgateNOTgateorinverter191.4ElectronicAspectsofDigitalDesign

（數(shù)字設(shè)計(jì)的電子技術(shù)）Howtorealizelogic0and1inarealcircuit?邏輯上的0和1在物理上如何實(shí)現(xiàn)？Whatistherangeofanalogvaluewitheachlogicvalue?什么電平范圍對(duì)應(yīng)邏輯0或1？Howtoproduceandfigureoutthesignalinaproperrange?如何正確產(chǎn)生和識(shí)別處于適當(dāng)范圍的信號(hào)？TheassociationbetweenDigitalandAnalog數(shù)字與模擬之間的關(guān)系201.5SoftwareAspectsofDigitalDesign*Whatdoessoftwarecando?Softwaretoolshelptoimprovethedesigner’sproductivity,thecorrectnessandqualitydesigns.軟件工具有助于提高設(shè)計(jì)的效率、正確性和質(zhì)量。SeveralSoftwareTools幾種軟件工具P9Pspise,multisim,電路仿真MaxPlus,QuatusII,VHDL仿真protel,powerPCB，制版軟件1.6IntegratedCircuits21Relay繼電器AdvancesofDigitalElectronictechnologies221.6IntegratedCircuitsAdvancesofDigitalElectronictechnologies數(shù)字電子技術(shù)的進(jìn)展20世紀(jì)40年代，賓夕法尼亞大學(xué)，第一部電子數(shù)字計(jì)算機(jī)（Eniac），采用真空管（VacuumTube）使用了17468個(gè)真空管占地457平米重30噸耗電160KW每秒可以完成5000次+，或385次*，或40次/，或3次開方運(yùn)算231.6IntegratedCircuits(集成電路IC)20世紀(jì)50年代（1947年），雙極型晶體管（BJT）出現(xiàn)；60年代，TTL邏輯出現(xiàn)，集成電路出現(xiàn)TTL:Transistor-TransistorLogic80年代開始，MOS電路開始逐步取代TTL電路，現(xiàn)在CMOS占領(lǐng)了世界IC市場(chǎng)的絕大部分CMOS:ComplementaryMOS241.6IntegratedCircuits單個(gè)硅片上的一個(gè)或多個(gè)門電路的集合體，就叫做集成電路。wafer(單晶硅片)

die(模片)packagingDualIn-line-pinPackage(DIP)雙列直插式封裝（P13）0.254mm15mm251.6IntegratedCircuits261.6IntegratedCircuitsSmall-ScaleIntegration(SSI，小規(guī)模集成):門1-20GatesMedium-ScaleIntegration(MSI，中規(guī)模集成):功能構(gòu)件20-200GatesLarge-ScaleIntegration(LSI，大規(guī)模集成):一個(gè)系統(tǒng)200-200,000GatesVeryLarge-ScaleIntegration(VLSI，超大規(guī)模集成):包含F(xiàn)PGA的系統(tǒng)Over1,000,000TransistorsSystemOnChip(SOC)片上系統(tǒng)集成系統(tǒng)TinyScaleIntegration(TSI)微小規(guī)模集成1.6IntegratedCircuitsJin.UESTC.27Question：Whatifthereissomethingwrongwiththealready-madeIC?Howtodebuggingit？Thesolutionis……ProgrammableLogicDevices（PLD）281.7ProgrammableLogicDevicesProgrammableLogicDevice(PLD,可編程邏輯器件)AND-ORcircuit1.7ProgrammableLogicDevicesProgrammableLogicArray(PLA,可編程邏輯陣列)ProgrammableArrayLogic(PAL,可編程陣列邏輯)ComplexPLD(CPLD,復(fù)雜可編程邏輯器件)Field-ProgrammableGateArray(FPGA,現(xiàn)場(chǎng)可編程門陣列）29301.8Application-SpecificICs

專用集成電路（ASIC）Semi-CustomIC(半定制IC)Non-RecurringEngineering(NRE)Cost(非再現(xiàn)工程成本）:$30,000-$50,000CustomIC(全定制IC）NRECost:Over$250,000Ifyouputthedesignintroducedinthistextbookintoapracticalchipmanufactory,you’rerequiringaASICproducing.311.9Printed-CircuitBoardsPrinted-WiringBoards(PWB,印制線路板)多層，1/16”鉆孔連線：10-50mil@3mil焊接1.9Printed-CircuitBoardsSurface-MountTechnology(SMT,表面安裝技術(shù))321.9Printed-CircuitBoardsMulti-ChipModule(MCM,多芯片模塊）Jin.UESTC.33MCM在多層印制板(PCB)和表面安裝技術(shù)(SMT)的基礎(chǔ)上發(fā)展起來(lái)的新一代微電子封裝與組裝技術(shù)，是實(shí)現(xiàn)系統(tǒng)集成的有力手段。信號(hào)傳輸速度、電性能以及可靠性等方面獨(dú)具優(yōu)勢(shì)，是目前能最大限度地提高集成度、提高高速單片IC性能，制作高速電子系統(tǒng)，實(shí)現(xiàn)整機(jī)小型化、多功能化、高可靠性、高性能的最有效途徑。341.10DigitalDesignLevelsDevicePhysicsandICManufacturingProcessesLevel（物理級(jí)：器件物理和IC制造過(guò)程）TransistorLevel（晶體管級(jí)）GatesStructureLevel（門電路結(jié)構(gòu)級(jí)）LogicDesignLevel（邏輯設(shè)計(jì)級(jí)）OverallSystemDesign（整體系統(tǒng)設(shè)計(jì)）本課程

*35Example:amultiplexerwith2datainputbitsABSZABSZ6transistors14transistorsHomework1.6以“數(shù)字電路設(shè)計(jì)的層次”為主題，標(biāo)題自擬，完成一篇2000~3000字左右的小論文。手寫、打印均可，下周四提交。3637DigitalLogicDesignandApplication

ChenYan

Lecture#2UESTC,Spring2011Chapter3DigitalCircuitsGiveaknowledgeoftheElectricalaspectsofDigitalCircuits

學(xué)習(xí)要求38掌握：CMOS邏輯電平和噪聲容限；CMOS邏輯基本門的電路結(jié)構(gòu);理解：CMOS邏輯電路的穩(wěn)態(tài)和動(dòng)態(tài)電氣特性；理解：特殊的輸入輸出電路結(jié)構(gòu);了解：利用仿真軟件對(duì)CMOS基本邏輯門的靜態(tài)特性和動(dòng)態(tài)特性進(jìn)行仿真。了解：作為電子開關(guān)運(yùn)用的二極管、雙極型晶體管、MOS場(chǎng)效應(yīng)管的工作方式；了解：其他類型的邏輯電路：TTL,ECL等；了解：不同類型、不同工作電壓的邏輯電路的輸入輸出邏輯電平規(guī)范值以及它們之間的連接配合的問(wèn)題。電路成本、速度與基本電路規(guī)模的關(guān)系。3.1LogicSignalsandGatesDigitlogichidethepitfallsoftheanalogworldbymappingtheinfinitesetofrealvaluesforaphysicalquantityintotwosubsetscorrespondingtojusttwopossiblenumbersorlogic：0an139InfiniteSignaloftherealworldTwovaluesintheDigitalLogicworldlogical

abstraction3.1LogicSignalsandGates40Tab.3-1themapingofpracticalphysicalsignaltothelogicalsignal玩過(guò)碟仙、筆仙的游戲嗎？3.1LogicSignalsandGates41Bufferamplifier1theminmialinputhighvoltagelevelvoltagelevelWeakstrong3.1LogicSignalsandGates423.1LogicSignalsandGatesMethodsofdescription,analysisanddesigntheabstractlogiccircuitsswitchingalgebraTruthtable/StateTable43X+X=XX*X=X……44AxiomsofLogicAlgebraX=0,ifX1(若X

1,則X=0)X=1,ifX0(若X

0,則X=1)

0’=1

1’=00·0=0 1+1=11·1=1 0+0=00·1=1·0=0 1+0=0+1=145BasicLogicFunction—AND000010100111ABZLogicEquationZ=A·BSwitch:1-on,0-offLamp:1-light,0-unlightedAnANDgateproducesa1outputifandonlyifallitsinputsare1.TruthTable&ABZABZLogicSymbolABZ46BasicLogicFunction:ORLogicEquation

:

Z=A+BABZTruthTableABZAnORgateproducesa1outputifandonlyifoneormoreinputsis1.000011101111≥1ABZABZLogicSymbol

47AZ0110TruthTableLogicEquationZ=A=A’AZRToproduceanoutputvaluethatistheoppositeofitsinputvalue.CommonlycalledanInverter.1ZAAZLogicSymbolBasicLogicFunction:NOT48TruthTable&≥1493.1LogicSignalsandGatesThephysicalaspectsofdigitalcircuitsPhysicalrealizationWorkingprinciplesElectricalcharactersChap.3503.1LogicSignalsandGatesHowtogettheHIGHandLOWVoltage?positivelogic10negativelogic10HighLowConsultFig.3-62forlogicalvoltagecomparetionVOUTVINVccR獲得高、低電平的基本原理513.2LogicFamiliesAlogicfamilyisacollectionofdifferentICchipsthathavesimilarinput,output,andinternalcircuitcharacteristics,butthatperformdifferentlogicfunctions.Chipsofsamefamilycanbeconnectedtoperformarbitarylogicfunction.(Fig.6-62)Chipsfromdifferentfamiliesmaynotbecompatible.TTLfamilies(Tab.3-10)CMOSlogic(Fig.3-62)52SomeTermsSemiconductordiode,半導(dǎo)體二極管Bipolarjunctiontransistor,雙極結(jié)型晶體管Integratedcircuit,集成電路Bipolarlogicfamily,雙極型邏輯系列Transistor-transistorlogic,TTL,晶體管-晶體管邏輯Metal-oxidesemiconductorfield-effecttransistor,MOSFET,金屬氧化物半導(dǎo)體場(chǎng)效應(yīng)晶體管ComplementaryMOS,CMOS,互補(bǔ)MOS533.3CMOSLogic1.CMOS

LogicLevelsLogic1(HIGH)

Logic0(LOW)5.0V3.5V1.5V0.0V

undefinedlogiclevel

ACMOSLogicCircuitusesnotonly5-Voltpower-supplyvoltage,butotherpower-supplyvoltages,suchas3.3,2.7volts.542.MOSTransistorsTwoTypes:N-ChannelandP-ChannelAninputvoltagecontrolstheresistancebetweendrainandsource.552.MOSTransistorsNormally,Vgs>=0IfVgs=0Rds

isveryhigh(>106?)

Thetransistoris“Off”.

increaseVgs

decreaseRds

whenRds

isverylow(<=10?)

thetransistoris“On”.Aninputvoltagecontrolstheresistancebetweendrainandsource.562.MOSTransistorsTwoTypes:P-ChannelNormally,

Vgs<=0If

Vgs=0Rds

isveryhigh.

Thetransistoris“Off”.Vgs

Rds

when

Rds

isverylow,

thetransistoris“On”.Aninputvoltagecontrolstheresistancebetweendrainandsource.注意，空穴的概念，以及空穴導(dǎo)電的實(shí)質(zhì)還是電子導(dǎo)電。2.MOSTransistorsTwoTypesMOS:N-ChannelandP-ChannelAninputvoltagecontrolstheresistancebetweendrainandsourceRgs、RgdisextremelyhighWhatevervoltageonGate，igs,igd

≈0(1μA）iscalledLeakagecurrent.TherearecapacitivecouplingbetweentheGate&Source,Gate&Drain5758BasicMOSon-offCircuitvI+–vO–+iD+VDDRDDGSQ1:CanwereplaceNMOSwithPMOS?Q2:HowtochoosetheloadresistanceRD?IfinputisL,transistoris“off”andoutputisH.

IfinputisH,transistoris“on”,outputisL.

593.BasicCMOSInverterCircuit1.VIN=0.0V(L)VGS1=0.0V，Q1

offVGS2=VIN–VDD=–5.0V,Q2onVOUT

VDD=5.0V(H)2.VIN=5.0V(H)VGS1=5.0V，Q1onVGS2=VIN–VDD=0.0V,Q2offVOUT

0.0V(L)VDD=+5.0VVOUTVINQ2p-channelQ1n-channelGDS2S160VDD=+5.0VVOUTVINQ2p-channelQ1n-channelSwitchmodel61CMOSinverterlogicaloperationVCCVinVoutONwheninputislow

ONwheninputishighVDD=+5.0VVOUTVINQ2p-channelQ1n-channel一個(gè)輸入同時(shí)控制兩個(gè)MOS管624.CMOSNANDGateUse2ntransistorsforn-inputgate1.Ifbothinputsarehigh,BothQ1andQ3are“on”,BothQ2andQ4are“off”,

Zislow(

0V).2.Ifeitherinputislow,eitherQ1orQ3is“off”,eitherQ2orQ4is“on”,Zishigh(

VDD).VDD=+5.0VZABQ1Q2Q4Q3634.CMOSNANDGateCMOSNANDmoreinputs(3)Can’tbeaddedunlimitedlyFanIn64Thenumberofinputsthatagatehaveiscalledfan-in.Theadditive“on”resistanceofseriestransistorslimitsthefan-inofCMOSgates.Gateswithalargenumberofinputscanbemadebycascading(級(jí)聯(lián))gateswithfewerinputs.654.CMOSNORGateLikeNAND―2ntransistorsforn-inputgate

1.Ifbothinputsarelow,bothQ1andQ3is“off”,bothQ2andQ4is“on”, Zishigh(

VDD).

2.Ifeitherinputishigh,eitherQ1orQ3is“on”,eitherQ2orQ4is“Off”,Zislow(0V).VDD=+5.0VZABQ1Q2Q4Q366NANDvs.NORForagivensiliconarea,PMOStransistorsare“weaker”thanNMOStransistors.Result:NANDgatesarepreferredinCMOS.675.CMOSAOIGatesZ=(A·B+C·D)’AND-OR-INVERT從NMOS的連接與邏輯“與”、“或”的關(guān)系來(lái)構(gòu)造；非是“免費(fèi)”獲得的VDD=+5.0VABZCD685.CMOSAOIGatesZ=(A·B+C·D)’696.Non-invertingGatesnoninvertingbuffer2-inputANDgateVDD=+5.0VAZIttypicallyisnotpossibletodesignanon-invertinggatewithasmallernumberoftransistorsthananinvertingone.Circuitdiagram:P94Figure3-197.BuildinganarbitarycircuitwithCMOS70每個(gè)CMOS門電路都由NMOS和PMOS兩部分組成，并且每個(gè)輸入都同時(shí)控制兩個(gè)管子；NMOS管串聯(lián)可實(shí)現(xiàn)與非操作，并聯(lián)可實(shí)現(xiàn)或非操作；PMOS管正好相反；NMOS管串聯(lián)時(shí)PMOS一定并聯(lián)；NMOS管并聯(lián)時(shí)PMOS一定串聯(lián)——對(duì)偶關(guān)系。PMOS網(wǎng)絡(luò)和NMOS網(wǎng)絡(luò)不能同時(shí)導(dǎo)通非是“免費(fèi)”獲得的課堂練習(xí)

CMOSOAIGates71F=((A+B)·(C+D))’Fig.3-22課堂練習(xí)72Z=(A’+B·C)’課堂練習(xí)73Z=A+B=A’·B+A·B’XORABZ000011101110A’ZBAB’A’ABB’課堂練習(xí)74(AOIGates)’Z=A’·B+A·B’=(A’·B+A·B’)’’=((A’·B+A·B’)’)’XORZ=(A·B+C·D)’753.7OtherCMOSInputandOutputStructures1.TransmissionGatesGates-CMOSTransmissionGatesWhenEN=0,EN_L=1,thetransistorsare“off”,AandBaredisconnected.WhenEN=1,EN_L=0,thetransistorsare“on”,

AandBareconnectedwithalow-impedance.

ENEN_LABBidirectionaldevice雙向器件門的導(dǎo)通時(shí)延大于傳輸時(shí)延3.7OtherCMOSInputandOutputStructures761.TransmissionGates-NMOS773.7OtherCMOSInputandOutputStructures1.TransmissionGates-PMOS0.1V0V0V0.1V0.1V0.1V0V0.2V0.1V0.2V3.7OtherCMOSInputandOutputStructuresApplicationofTransmissionGates78s’Fig.3-46ZSVCCXYMUX(Multiplexer)s’s’X

YssZ=S’·X+S·Y

010011S=0;T1on,T2off;Z=XS=1;T1off,T2On;Z=Y

ZYXST1T2792.

Three-StateOutputsVCCZENAIfEN=0,C=1,Tp=“off”B=1,D=0,Tn=“off”

Z=Hi-impedancestateor

floatingstateIfEN=1C=A’,B=0,D=A’

Z=A(0or1)BCDTpTnAENOUTLogicSymbol還有很多其他三態(tài)緩沖器件類型，其應(yīng)用主要是三態(tài)總線803.

Open-DrainOutputsABZVCCVCC’Rpull-upresistanceABZLogicSymbolAssmallaspossible,tominimizetherisetime.Cannotbearbitrarilysmall,itisdeterminedbyIOLmaxpassivepull-up無(wú)源上拉Applications:drivingmultisourcebuses;drivingLEDs;performingwiredlogic.

3.

Open-DrainOutputs81Pull-upresistorvalue上拉電阻阻值的范圍ABZVCCRRMin=VCC-VOLMax

iRiR=IOLMax-iLRmax=VCC-VOHMiniRiR=iLeak+iLVout=Rn

Rn+RVCCLH3.

Open-DrainOutputs

DrivingLEDsLED點(diǎn)亮的條件是：使Vz為低電壓，與Vcc有1.6V的電壓差，并且保證ILED≥10mA82VOLmaxVCC=VLED+VOL+VR=VLED+VOL+R*ILEDR

=VCC-VLED-VOLMaxILEDmin833.

Open-DrainOutputs

Multi-sourceBuses84ABZVCCVCCRCDVCCZ=Z1·Z2=(A·B)’·(C·D)’=(A·B+C·D)’WiredLogicofOpen-DrainOutputsZ1Z2WiredAND(線與)第4章反演定理852.輸出電平？？造成邏輯混亂1.很大的負(fù)載電流同時(shí)流過(guò)輸出級(jí)可使門電路損壞3.

Open-DrainOutputsVCCAZactivepull-up有源上拉VCCB低高有源上拉的CMOS器件其輸出端不能直接相聯(lián)100

>1M

100

>1M

Fighting沖突864.Schmitt-TriggerInputsVOUTVIN5.02.12.95.0I-OtransfercharacteristicVT+VT-inputswitching

thresholdVT+VT-Usefeedbackinternallyshifttheswitchingthreshold.采用內(nèi)部反饋，邊沿更陡Hysteresis(滯后):thedifferencebetweenthetwothresholds.LogicSymbol:87ApplicationsofSchmitt-Trigger波形變換VT88ApplicationsofSchmitt-Trigger脈沖整形89ApplicationsofSchmitt-Trigger脈沖鑒幅Backups9091DigitalLogicDesignandApplication

ChenYan

Lecture#3CMOSElectricalBehaviorUESTC,Spring201192LastLecturePositiveLogicandNegativeLogicCMOSLogic93LastLectureNAND,NOR,AOI,OAI2ntransistorsforn-inputgateNotice:theadditive“on”resistanceoftransistorsPMOS網(wǎng)絡(luò)NMOS網(wǎng)絡(luò)OutI1InI1In……LastLectureTransmissionGatesTri-StategatesDrainopengatesSchmitt-triggerinput94953.4ElectricalBehaviorofCMOSCircuitsDigitalanalysisworksonlyifcircuitsareoperatedinspec:PowersupplyvoltageTemperatureInput-signalqualityOutputloadingMustdosome“analog”analysistoprovethatcircuitsareoperatedinspec.Fan-inspecsFan-outspecsTiminganalysis(setupandholdtimes)963.4ElectricalBehaviorofCMOSCircuitsOverviewLogicVoltageLevelsDCNoiseMarginsFan-OutSpeedPowerConsumptionNoiseElectrostaticDischarge(靜電放電)Open-DrainOutputsThreeStateOutputsnotlogical973.4ElectronicBehaviorofCMOSCircuitsANANDGateDataSheetsandSpecifications(P99Table3-3)983.5CMOSSteady-StateElectricalBehavior3.5.1LogicLevelsandNoiseMarginsVDD=+5.0VVOUTVINTpTn0101991003.5CMOSSteady-StateElectricalBehavior3.5.1LogicLevelsSpecificationsHIGHABNOMALLOWVOLmaxVOHminTheinputvoltagesaredeterminedmainlybyswitchingthresholdsofthetransistors,whiletheoutputvoltagesaredeterminedmainlybythe“on”resistanceofthetransistors.VILmaxVIHminVCC?0.1VGND+0.1V70%VCC30%VCCPower-supplyrails:VCCandGND1013.5.1DCNoiseMargin30%VCC?0.1VHIGHABNOMALLOWVOLmaxVILmaxVIHminVOHminHigh-stateDCnoisemarginLow-stateDCnoisemargin3.5CMOSSteady-StateElectricalBehavior3.5.2CircuitBehaviorwithResistiveLoadsResistiveLoadsdiscreteresistorTTLandothernon-CMOSloadCurrentconsumptiondevice102whichrequirenontrivialamountsofcurrenttooperateCMOSdevicehasveryhighinputimpedance,itbehavesasideallogicdevice.3.5.2CircuitBehaviorwithResistiveLoads103WhentheoutputofCMOScircuitisconnectedtoaresistiveload,theoutputbehaviorisnotasidealaswedescribedpreviously.Theonresistor(non-zero)willleadtoanon-zerovoltagedropwhichwillcausetheL-outputvoltagegreaterthanVOLMax

ortheH-outputvoltagelowerthanVOHMin.UseresistivemodeltoanalysistheCMOScircuitbehaviorwithresistiveloads.任何只包含電壓源和電阻的雙端網(wǎng)絡(luò)，可由一個(gè)電壓源和一個(gè)電阻串聯(lián)組成的戴文寧等效電路進(jìn)行模型化。所有獨(dú)立源為零值時(shí)所得的網(wǎng)絡(luò)求等效電阻時(shí)，電壓源用短路代替1043.5.2CircuitBehaviorwithResistiveLoadsVCCAZresistivemodel105VCC=+5.0VRp>1M

RnResistiveLoadVOLmaxIOLmaxWhenoutputisLOW,VOUT<=VOLmaxthecurrentflowsfromthepowersupply,throughtheloadandthroughthedeviceoutputtoground.Thedeviceoutputissaidtosinkcurrent(灌電流).IOLmax:ThemaximumcurrenttheoutputcansinkintheLOWstatewhilestillmaintaininganoutputvoltagenogreaterthanVOLmax.106VCC=+5.0VRpRn>1M

ResistiveLoadVOHminIOHmaxWhenoutputisHIGH,VOUT>=VOHminthecurrentflowsfromthepowersupply,outofthedeviceoutputandthroughtheloadtoground.Thedeviceoutputissaidtosourcecurrent(拉電流).IOHmax:ThemaximumcurrenttheoutputcansourceintheHIGHstatewhilestillmaintaininganoutputvoltagenogreaterthanVOHmin.107Output-voltagedropResistanceof“off”transistoris>1Megohm,butresistanceof“on”transistorisnonzero,Voltagedropsacross“on”transistor,V=IRFor“CMOS”loads,currentandvoltagedroparenegligible.ForTTLinputs,LEDsterminations,orotherresistiveloads,currentandvoltagedroparesignificantandmustbecalculated.108VOUT=0VCC=+5.0VRThevVThev

+VIN=1WiththeoutputLOW,theestimatesinkcurrentisVCC=+5.0VRThevVThev

+VOUT=1VIN=0WiththeoutputHIGH,theestimatedsourcecurrentisIdealBehavior1093.5.3CircuitBehaviorwithNonidealInputsVCC=+5.0V400

2.5k

VIN1.5VVOUT4.31VVCC=+5.0V4k

200

VIN3.5VVOUT0.24VTheoutputvoltagedeterioratesfurtherwitharesistiveload.What’sworseis:Outputcurrent

,PowerConsumption

Ideal:CMOSpowerconsumptionisaboutμW.awayfromthepower-supplyrailP=8.62mW1103.5.4FanoutThenumberofinputsthatthegatecandrivewithoutexceedingitsworst-caseloadingspecifications.在不超出其最壞情況負(fù)載規(guī)格的條件下，一個(gè)邏輯門能驅(qū)動(dòng)的輸入端個(gè)數(shù)。Fanoutmustbeexaminedforbothpossibleoutputstates,HIGNandLOW.

overallfanout=min(HIGH-state,LOW-statefanout)DCfanoutandACfanout111LOWstateFan-OutExample:computethefan-outfor74HCTdriving74LS

HIGHstateFan-OutCMOS:74HCTIOH=–4mAIOL=4mAIIH=1

AIIL=–1

ATTL:74LSIOH=–400

AIOL=8mAIIH=20

AIIL=–0.4mA總扇出

HIGHstate剩余驅(qū)動(dòng)能力：1123.5.5EffectsofLoadingLoadinganoutputbeyonditsrated(額定的)

fanouthasseveraleffects:

(P111)Theoutputvoltagemaydeteriorate.Thepropagationdelay,outputriseandfalltimemayincreasebeyondtheirspecifications.Theoperatingtemperatureofthedevicemayincrease,therebyreducingreliabilityandcausingdevicefailure.1133.5.6UnusedInputsUnusedCMOSinputshouldneverbeleftunconnected(orfloating).XZTodothisincreasethecapacitiveloadonthedrivingsignalandmayslowthingsdown.增加了驅(qū)動(dòng)信號(hào)的電容負(fù)載，使操作變慢XZ1k+5Vlogic1XZlogic03.5.6HowtodestroyaCMOSdeviceStraycapacitance(寄生電容)Electrostaticdischarge(ESD靜電放電)114+-1153.6CMOSDynamicElectricalBehaviorBoththespeedandthepowerconsumptionofaCMOSdevicedependtoalargeextentondynamiccharacteristicsofthedeviceanditsload.Speeddependsontwocharacteristics:TransitionTime

(轉(zhuǎn)換時(shí)間)Theamountoftimethattheoutputofalogiccircuittakestochangefromonestatetoanother.PropagationDelay

(傳播延遲)Theamountoftimethatittakesforachangeintheinputsignaltoproduceachangeintheoutputsignal.3.6CMOSDynamicElectricalBehaviorStraycapacitance(寄生電容)Jin.UESTC1161173.6.1TransitionTimetrtftrtfHIGHLOWVIHminVILmaxRisetimetrFalltimetf

Tr=

TOHmin-TOLMaxTf=TOLMax-TOHmin1183.6.1TransitionTimeDependontwofactors:“On”resistanceoftransistorcapacitance(電容)VCC=+5.0VRLRpRnVL+CLInrealdigitalcircuit,thetransitiontimeapproximatelyequalstheRCtimeconstant.Fig.3-38計(jì)算CMOS的上升和下降時(shí)間1193.6.2PropagationDelayVIN50%VOUTSignalpathpropagationdelaytpistheamountoftimethatittakesforachangeintheinputsignaltoproduceachangeintheoutputsignal.Quiz：tr，tf包含在Tp中嗎？

50%50%50%1203.6.3PowerConsumptionPT:thepartialshort-circuitingoftheCMOSoutputstructurePL:thecapacitiveloadontheoutputStatic/QuiescentPowerDissipationEitheroneofthetwoMOSTransistorsisoff,ids=ileak

DynamicPowerDissipationVDD=+5.0VVOUTVINTpTnCLPowerdissipationcapacitance功耗電容1213.6.4CurrentSpikesanddecouplingCapacitors電流尖峰和去藕電容器電流傳輸特性iDvI12VDDCMOS反相器只在PMOS和NMOS管都處于飽和導(dǎo)通狀態(tài)，才會(huì)產(chǎn)生較大的電流，其他情況電流都極小。Jin.UESTC1223.8CMOSLogicFamilies7454PartNumber:

FAMnn

functionHCandHCT(High-speedCMOS,TTLcompatible)Jin.UESTC1233.8CMOSLogicFamiliesAHCandAHCT(A—advanced)*HC（T）*ElectricalCharacteristicsP144Table3-5,P146Table3-6,P147Table3-7Symmetricoutputdrive

(對(duì)稱的輸出驅(qū)動(dòng)) outputcansinkorsourceequalamountsofcurrentACandACTFCTandFCT-TFCT-TElectricalCharacteristicsJin.UESTC1243.9Low-VoltageCMOSLogicandInterfacingWhyLow-Voltage？125電路類型電源電壓/V傳輸延遲時(shí)間/ns靜態(tài)功耗/mW功耗－延遲積/mW-ns直流噪聲容限輸出邏輯擺幅/VVNL/VVNH/VTTLCT54/74＋510151501.22.23.5CT54LS/74LS＋57.52150.40.53.5HTL＋158530255077.513ECLCE10K系列－5.2225500.1550.1250.8CE100K系列－4.50.7540300.1350.1300.8CMOSVDD=5V＋5455×10－3225×10－32.23.45VDD=15V＋151215×10－3180×10－36.59.015高速CMOS＋581×10－38×10－31.01.55各類數(shù)字集成電路主要性能參數(shù)的比較126QuizA74LS00hasVOHmin=2.7V,VOLmax=0.5V,VIHmin=2.0V,VILmax=0.8V,determinetheworst-caseLOW-stateandHIGH-stateDCnoisemarginsofthe74LS00.Backups127128Chapter3Task（P175~180）3.1(a)(e)(h)3.2(a)(e)(h)3.53.93.163.173.183.27(d)3.28(自學(xué)3.5.8)3.37理解3.393.423.473.49(a)(b)3.57(a)3.53P167Table3-103.56(c)3.613.62

3.81129Chapter3TaskP175~1803.1(a)(e)(h)3.2(a)(e)(h)3.53.93.163.27(d)3.37理解3.393.423.47計(jì)算扇出3.49(a)(b)3.57(a)計(jì)算直流噪聲容限3.533.56(c)選做3.613.623.813.28(自學(xué)3.5.8)130DigitalLogicDesignandApplication

Lecture#4Chap.2NumbersystemsandCodesUESTC,Spring2013Introduction所有信息都可以用有限位的二進(jìn)制數(shù)字表示，因此數(shù)字系統(tǒng)可以處理任何信息。如何用二進(jìn)制數(shù)字量來(lái)表示、運(yùn)算信息模擬量有正、負(fù)之分模擬量有整、零之別除了二進(jìn)制還有其他表示方法嗎不能或不便抽象為兩值子集的信息如何處理？131學(xué)習(xí)要求掌握：十進(jìn)制、二進(jìn)制、八進(jìn)制和十六進(jìn)制數(shù)的表示方法以及它們之間的相互轉(zhuǎn)換、二進(jìn)制數(shù)的運(yùn)算；符號(hào)數(shù)的表達(dá)：符號(hào)-數(shù)值碼（Signed-MagnitudeSystem、原碼），二進(jìn)制補(bǔ)碼(two'scomplement，補(bǔ)碼)、二進(jìn)制反碼（ones'complement,反碼）表示以及它們之間的相互轉(zhuǎn)換；符號(hào)數(shù)的運(yùn)算；溢出的概念。掌握：其他信息的編碼表達(dá)：BCD碼（BinaryCodesforDecimalnumbers）、n中取1碼（獨(dú)熱碼）、格雷碼（Graycode）的特點(diǎn)及其與二進(jìn)制數(shù)之間的轉(zhuǎn)換關(guān)系；了解：模擬信息的數(shù)字表達(dá)：A/D轉(zhuǎn)換的基本概念；了解：字符的代碼表示，二進(jìn)制代碼在狀態(tài)、條件等的表示方面的應(yīng)用；1322.1PositionalNumbersystem用進(jìn)位的方法進(jìn)行計(jì)數(shù)的數(shù)制稱為進(jìn)位計(jì)數(shù)制(或按位計(jì)數(shù)制PositionalNumbersystem)。133DigitRadixNumberWeightedsumofthedigits.Weight2.1PositionalNumbersystem134數(shù)制的三要素為：數(shù)碼(digit)：0~r-1，進(jìn)位規(guī)律：逢r進(jìn)一，借一當(dāng)r?；鶖?shù)(base/radix)：數(shù)碼的進(jìn)制數(shù)r，也稱為基數(shù)（底數(shù)）。位權(quán)(weight)：ri，數(shù)碼在一個(gè)數(shù)中的位置不同，其大小就不同。i是數(shù)碼所在的位置，稱為數(shù)位。2.1PositionalNumbersystemDecimal（十進(jìn)制）Digit：0~9，逢10進(jìn)1，借1當(dāng)10Weight：(10)10

iRadix：10

2.1PositionalNumbersystemBinary

(二進(jìn)制)Digit：0~1，逢2進(jìn)1，借一當(dāng)2Weight：(2)10

iRadix：2二進(jìn)制的優(yōu)點(diǎn)：運(yùn)算簡(jiǎn)單，電路簡(jiǎn)單，工作可靠。數(shù)字電路中多使用二進(jìn)制.二進(jìn)制的不足：一個(gè)較大的十進(jìn)制用二進(jìn)制表示需要較多的位，為了克服二進(jìn)制書寫太長(zhǎng)的缺點(diǎn)，常用八進(jìn)制和十六進(jìn)制。2.1PositionalNumbersystemOctal（八進(jìn)制）Digit：0~7，逢8進(jìn)1，借1當(dāng)8Weight：(8)10

iRadix：8

Hexadecimal（十六進(jìn)制）Digit：0~9A~F（10~15)，逢16進(jìn)1，借1當(dāng)16Weight：(16)10

i