HZHY-AL200-硬件設(shè)計-數(shù)據(jù)手冊-tca9554a

Sample&

Tools&

Support&SCPS196D–DECEMBER2010–REVISEDAUGUSTTCA9554ALowVoltage8-BitI2CandSMBusLow-PowerI/OExpanderWithInterruptOutputandConfigurationRegisters I2CtoParallelPortOpen-DrainActive-LowInterrupt

TheTCA9554Aisa16-pindevicethatprovides8bitsofgeneralpurposeparallelinput/output(I/O)expansionforthetwo-linebidirectionalI2Cbus(orOperatingPower-SupplyVoltageRangeof1.65 SMBus)protocol.Thedevicecanoperatewithto5.5 powersupplyvoltagerangingfrom1.65Vto5.55-VTolerantI/O400-kHzFastI2C

Thedevicesupportsboth100-kHz(Standard-mode)and400-kHz(Fast-mode)clockfrequencies.I/OexpanderssuchastheTCA9554AprovideaThreeHardwareAddressPinsAllowupto Devicesonthe switches,sensors,push-buttons,LEDs,fans,Input/OutputConfiguration

othersimilarPolarityInversion ThefeaturesoftheTCA9554AincludeanInternalPower-OnLowStandbyCurrent

thatisgeneratedontheINTpinwheneveraninputportchangesstate.TheA0,A1,andA2hardwareselectableaddresspinsallowuptoeightPower-UpWithAllChannelsConfiguredas devicesonthesameI2Cbus.ThedevicecanalsoNoGlitchonPowerNoiseFilteronSCL/SDA

resettoitsdefaultsatebycyclingthepowersupplyandcausingapower-onreset.LatchedOutputsWithHigh-Current DevicePARTBODYSIZETSSOP5.00PARTBODYSIZETSSOP5.00mm×4.40SSOP4.90mm×3.90SSOP6.20mm×5.30Latch-UpPerformanceExceeds100mAPerJESD78,ClassIIESDProtectionExceedsJESD2000-VHuman-BodyModel(A114- (1)Forallavailablepackages,seetheorderableaddendum1000-VCharged-DeviceModelRouters(TelecomSwitchingPersonalPersonalElectronics(e.g.GamingIndustrialProductsWithGPIO-Limited

theendoftheSimplifiedBlockENABLE,orINTor(e.g.AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,AnIMPORTANTNOTICEattheendofthisdatasheetaddressesavailability,warranty,changes,useinsafety-criticalapplications,intellectualpropertymattersandotherimportantdisclaimers.PRODUCTIONDATA.SCPS196DSCPS196D–DECEMBER2010–REVISEDAUGUSTSCPS196DSCPS196D–DECEMBER2010–REVISEDAUGUSTSubmitDocumentationSubmitDocumentationCopyright?2010–2015,TexasInstrumentsProductFolderLinks:SubmitDocumentationSubmitDocumentationCopyright?2010–2015,TexasInstrumentsProductFolderLinks:Tableof Revision PinConfigurationand AbsoluteMaximum ESD RecommendedOperating Thermal Electrical I2CInterfaceTiming Switching Typical ParameterMeasurement Detailed FunctionalBlock

Feature DeviceFunctional Register Applicationand Application Typical PowerSupply Power-OnReset Layout Layout DeviceandDocumentation Community ElectrostaticDischarge Mechanical,Packaging,andOrderable RevisionChangesfromRevisionC(May2015)toRevision AddedDB ChangesfromRevisionB(October2014)toRevision AddedstandbymodecurrentforVI=VCCtest ChangedΔICCforoneP-portinputatVI=VCC-0.6,andotherP-portI/OatVI=VCCor AddedclarificationindatasheetthatraisingvoltageaboveVCConP-portI/OwillresultincurrentflowfromP-port ChangesfromRevisionA(March2012)toRevision AddedHandlingRatingtable,FeatureDescriptionsection,DeviceFunctionalModes,ApplicationandImplementationsection,PowerSupplyRecommendationssection,Layoutsection,DeviceandDocumentationSupportsection,andMechanical,Packaging,andOrderableInformation UpdatedIOLPARAMETERintheElectricalCharacteristics ChangesfromOriginal(August2014)toRevision Initialreleaseoffull UpdatedpartnumberintheDESCRIPTION/ORDERINGINFORMATION PinConfigurationand(TOPVIEW)Pin1IAddressinput.ConnectdirectlytoVCCor2IAddressinput.ConnectdirectlytoVCCor3IAddressinput.ConnectdirectlytoVCCor4P-portinput/output.Push-pulldesignstructure.Atpoweron,P0isconfiguredasaninput.5P-portinput/output.Push-pulldesignstructure.Atpoweron,P1isconfiguredasaninput.6P-portinput/output.Push-pulldesignstructure.Atpoweron,P2isconfiguredasaninput.7P-portinput/output.Push-pulldesignstructure.Atpoweron,P3isconfiguredasaninput.8–9P-portinput/output.Push-pulldesignstructure.Atpoweron,P4isconfiguredasaninput.P-portinput/output.Push-pulldesignstructure.Atpoweron,P5isconfiguredasaninput.P-portinput/output.Push-pulldesignstructure.Atpoweron,P6isconfiguredasaninput.P-portinput/output.Push-pulldesignstructure.Atpoweron,P7isconfiguredasaninput.OInterruptoutput.ConnecttoVCCthroughapull-upISerialclockbus.ConnecttoVCCthroughapull-upSerialdatabus.ConnecttoVCCthroughapull-up–SupplyAbsoluteMaximumoveroperatingfree-airtemperaturerange(unlessotherwiseSupplyvoltage6VInputvoltage6VOutputvoltage6VInputclampVI<OutputclampVO<Input/outputclampVO<0orVO>ContinuousoutputlowcurrentthroughasingleP-VO=0toContinuousoutputhighcurrentthroughasingleP-VO=0toContinuouscurrentthroughGNDbyallP-ports,INT,andContinuouscurrentthroughVCCbyallP-StoragetemperatureStressesbeyondthoselistedunder"absolutemaximumratings"maycausepermanentdamagetothedevice.Thesearestressratingsonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedunder"recommendedoperatingconditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmayaffectdevicereliability.Theinputnegative-voltageandoutputvoltageratingsmaybeexceedediftheinputandoutputcurrentratingsareESD ElectrostaticHuman-bodymodel(HBM),perANSI/ESDA/JEDECJS-VCharged-devicemodel(CDM),perJEDECspecificationJESD22-JEDECdocumentJEP155statesthat500-VHBMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwithlessthan500-VHBMispossiblewiththenecessaryprecautions.JEDECdocumentJEP157statesthat250-VCDMallowssafemanufacturingwithastandardESDcontrolprocess.Manufacturingwithlessthan250-VCDMispossiblewiththenecessaryprecautions.RecommendedOperatingSupplyVHigh-levelinputSCL,VCC=1.65Vto5.50.7×VA2–A0,VCC=1.65Vto2.70.7×VCC=3.0Vto5.50.8×Low-levelinputSCL,VCC=1.65Vto5.50.3×VA2–A0,VCC=1.65Vto2.70.3×VCC=3.0Vto5.50.2×High-leveloutputAnyP-port,Low-leveloutputAnyP-port,ContinuouscurrentthroughAllP-portsP7-P0,INT,andContinuouscurrentthroughAllP-portsP7-Operatingfree-air(1)TheSCLandSDApinsshallnotbeatahigherpotentialthanthesupplyvoltageVCCintheapplication,oranincreaseinleakagecurrent,II,willresult.ThermalTHERMALPWDBQDB161616 Junction-to-ambientthermal Junction-to-case(top)thermal Junction-to-boardthermal Junction-to-topcharacterization Junction-to-boardcharacterization(1)Formoreinformationabouttraditionalandnewthermalmetrics,seetheSemiconductorandICPackageThermalMetricsapplicationreport,SPRA953.Electricaloveroperatingfree-airtemperaturerange(unlessotherwiseTESTInputdiodeclampII=–181.65Vto5.5VPower-onresetvoltage,VCCVI=VCCorGND,IO=VPower-onresetvoltage,VCCVI=VCCorGND,IO=VP-porthigh-leveloutputIOH=–81.65V2.334.5IOH=–101.652.334.5VOL=0.41.65Vto5.53PVOL=0.51.6582.38384.58VOL=0.71.652.334.5INTVOL=0.41.65Vto5.537SCL,VI=VCCor1.65Vto5.5PVI=1.65Vto5.51PVI=1.65Vto5.5Alltypicalvaluesareatnominalsupplyvoltage(1.8V,2.5V,3.3V,or5VVCC)andTA=EachP-portI/Oconfiguredasahighoutputmustbeexternallylimitedtoamaximumof10mA,andthetotalcurrentsourcedbyallI/Os(P-portsP7-P0)throughVCCshouldbelimitedtoamaximumcurrentof80mA.TheSDApinmustbeexternallylimitedtoamaximumof12mA,andthetotalcurrentsunkbyallI/Os(P-portsP7-P0,INT,andSDA)throughGNDshouldbelimitedtoamaximumcurrentof200mA.EachP-portI/Oconfiguredasalowoutputmustbeexternallylimitedtoamaximumof25mA,andthetotalcurrentsunkbyallI/Os(P-portsP7-P0,INT,andSDA)throughGNDshouldbelimitedtoamaximumcurrentof200mA.TheINTpinmustbeexternallylimitedtoamaximumof7mA,andthetotalcurrentsunkbyallI/Os(P-portsP7-P0,INT,andSDA)throughGNDshouldbelimitedtoamaximumcurrentof200mA.ElectricalCharacteristicsoveroperatingfree-airtemperaturerange(unlessotherwiseTESTOperatingAllP-portI/OatVI=VCCorGND(6),IO=I/O=inputs,fscl=400kHz,Noloadtr=3ns5.5AllP-portI/OatVI=VCCorGND(6),IO=I/O=inputs,fscl=400kHz,Noloadtr,max=300ns5.53.62.795AllP-portI/OatVI=VCCorGND(6),IO=I/O=inputs,fscl=100kHztr,max=1μs5.53.682.751.653StandbyAllP-portI/OatVI=VCC,IO=0,I/O=inputs,fscl=0kHz,Noload5.53.62.71.65AllP-portI/OatVI=GND,IO=0,I/O=inputs,fscl=0kHz,No5.53.62.71.95Supplycurrentincrease(instandbymode)withoneI/Oinputatspecifiedvoltagelevel,ratherthanGNDorVCCOneP-portI/OatVI=VCC–0.6V,OtherP-portI/OatVI=VCCor1.65Vto5.5VI=VCCor1.65Vto5.545VIO=VCCor1.65Vto5.5P8Thecurrentthroughtheintegratedpull-upresistorhasbeensubtractedfromtheICCoperatingmodecurrentforVI=GNDI2CInterfaceTimingoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigureSTANDARDMODEI2CBUSFASTMODEI2CBUSI2Cclock00I2Cclockhigh4I2CclocklowI2CspikeI2Cserial-datasetupI2Cserial-datahold00I2CinputriseI2Cinputfall20×(VDD/5.5I2Coutputfall10-pFto400-pF20×(VDD/5.5I2CbusfreetimebetweenstopandI2CstartorrepeatedstartconditionI2Cstartorrepeatedstartcondition4I2Cstopcondition4ValiddataSCLlowtoSDAoutputValiddatatimeofACKconditionACKsignalfromSCLlowtoSDA(out)lowI2CbuscapacitiveSwitchingoveroperatingfree-airtemperaturerange(unlessotherwisenoted)(seeFigure11andFigureSTANDARDMODEI2CBUSFASTMODEI2CBUS InterruptvalidP44 Interruptresetdelay44 Outputdata InputdatasetupP InputdataholdP11TypicalTA=25°C(unlessotherwise1.8 2.5ICC-SupplyICC-SupplyCurrent 586420

10

5- - - - TA-Free-AirTemperaturefSCL=400 I/Os=HighorFigure1.SupplyCurrent(ICC,OperatingMode)Temperature(TA)atFourSupply

TA-Free-AirTemperaturefSCL=0 I/Os=HighFigure2.SupplyCurrent(ICC,StandbyMode)Temperature(TA)atFourSupply

ICC-ICC-SupplyCurrent 50

0- -

VCC=1.8V,IOL=8mAVCC=5V,IOL=8mAVCC=1.8V,IOL=10mAVCC=5V,IOL=10mA VCC-SupplyVoltage

TA-Free-AirTemperature

fSCL=400 I/Os=Highor TA=Figure3.SupplyCurrent(ICC,OperatingMode)vs.SupplyVoltage(VCC)1.8

Figure4.OutputLowVoltage(VOL)vs.Temperature(TA)forP-PortI/OsVCCVCC=1.8V,IOH=8mAVCC=5V,IOH=8mAVCC=1.65V,IOH=10mAVCC=5V,IOH=10mAIOL-OutputIOL-OutputSinkCurrent3.3 50

0- -

TA=

VOL-OutputLowVoltage-

TA-Free-AirTemperature

Figure5.SinkCurrent(IOL)vs.OutputLowVoltage(VOL)forP-PortsatFourSupplyVoltages

Figure6.OutputHighVoltage(VCC-VOH)vs.Temperature(TA)forP-Ports554321 =-800 0123IOH=-10 (VCC-VOH)-OutputHighVoltageTA=VCC-SupplyVoltage6Figure7.SourceCurrent(IOH)vs.OutputHighVoltage(VOH)forP-PortsatFourSupplyVoltages0TA=Figure8.OutputHighVoltage(VOH)vs.SupplyVoltage(VCC)forP-Ports- NumberofI/OsHeldLow8VCC=5Figure9.SupplyCurrent(ICC)vs.NumberofI/OsHeldLowIOH-OutputSourceCurrentParameterMeasurementCLincludesprobeandjigAllinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,ZO=50?,tr/tf≤30AllparametersandwaveformsarenotapplicabletoallFigure10.I2CInterfaceLoadCircuitAndVoltageParameterMeasurementInformation

RL=4.7CL=100(seeNote0.7x

0.7x

0.3x

0.3xPort

0.7x0.3x

0.7x0.3xCLincludesprobeandjigAllinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,ZO=50?,tr/tf≤30AllparametersandwaveformsarenotapplicabletoallFigure11.InterruptLoadCircuitAndVoltageParameterMeasurementInformationCLincludesprobeandjigtpvismeasuredfrom0.7×VCConSCLto50%I/O(Pn)Allinputsaresuppliedbygeneratorshavingthefollowingcharacteristics:PRR≤10MHz,ZO=50?,tr/tf≤30Theoutputsaremeasuredoneatatime,withonetransitionperAllparametersandwaveformsarenotapplicabletoallFigure12.P-PortLoadCircuitAndVoltageDetailedTheTCA9554Aisan8-bitI/Oexpanderforthetwo-linebidirectionalbus(I2C)isdesignedfor1.65-Vto5.5-VVCCoperation.Itprovidesgeneral-purposeremoteI/Oexpansionformostmicro-controllerfamiliesviatheI2Cinterface(serialclock,SCL,andserialdata,SDA,pins).TheTCA9554Aopen-draininterrupt(INT)outputisactivatedwhenanyinputstatediffersfromitscorrespondingInputPortregisterstateandisusedtoindicatetothesystemmasterthataninputstatehaschanged.TheINTpincanbeconnectedtotheinterruptinputofamicro-controller.Bysendinganinterruptsignalonthisline,theremoteI/Ocaninformthemicro-controllerifthereisincomingdataonitsportswithouthavingtocommunicateviatheI2Cbus.Thus,theTCA9554Acanremainasimpleslavedevice.Thedeviceoutputs(latched)havehigh-currentdrivecapabilityfordirectlydrivingLEDs.Threehardwarepins(A0,A1,andA2)areusedtoprogramandvarythefixedI2CslaveaddressandallowuptoeightdevicestosharethesameI2CbusorSMBus.ThesystemmastercanresettheTCA9554Aintheeventofatimeoutorotherimproperoperationbycyclingthepowersupplyandcausingapower-onreset(POR).AresetputstheregistersintheirdefaultstateandinitializestheI2C/SMBusstatemachine.TheTCA9554Aconsistsofone8-bitConfiguration(inputoroutputselection),InputPort,OutputPort,andPolarityInversion(activehighoractivelow)registers.Atpoweron,theI/Osareconfiguredasinputs.However,thesystemmastercanenabletheI/OsaseitherinputsoroutputsbywritingtotheI/Oconfigurationbits.ThedataforeachinputoroutputiskeptinthecorrespondingInputPortorOutputPortregister.ThepolarityoftheInputPortregistercanbeinvertedwiththePolarityInversionregister.Allregisterscanbereadbythesystemmaster.TheTCA9554AandTCA9554areidenticalexceptfortheirfixedI2Caddress.Thisallowsforupto16ofthesedevices(8ofeach)onthesameI2C/SMBus.TheTCA9554AisidenticaltotheTCA9534AexceptfortheadditionoftheinternalI/Opull-upresistors,whichkeepsP-portsfromfloatingwhenconfiguredasinputs.FunctionalBlockLP123I2C8Power-Read PinnumbersshownareforthePWFigure13.FunctionalBlockFunctionalBlockDiagramDataDataShiftShift Output100Configuration KQDCKP0toESDInputInputReadDCKDataShiftDCKAtpower-onreset,allregistersreturntodefaultFigure14.SimplifiedSchematicOfP0ToFeatureI/OWhenanI/Oisconfiguredasaninput,FETsQ1andQ2areoff,creatingahigh-impedanceinputwithaweakpull-up(100k?typ)toVCC.TheinputvoltagemayberaisedaboveVCCtoamaximumof5.5V,howeveritmustbenotedthatbecauseoftheintegrated100kΩpull-upresistoritmayresultincurrentflowfromI/OtoVCCpin(Figure14).IftheI/Oisconfiguredasanoutput,Q1orQ2isenableddependingonthestateoftheoutputportregister.Inthiscase,therearelowimpedancepathsbetweentheI/OpinandeitherVCCorGND.TheexternalvoltageappliedtothisI/Opinshouldnotexceedtherecommendedlevelsforproperoperation.InterruptOutputAninterruptisgeneratedbyanyrisingorfallingedgeofanyP-portI/Oconfiguredasaninput.Aftertimetiv,thesignalINTisvalid.ResettingtheinterruptcircuitisachievedwhendataontheportsischangedbacktotheoriginalstateorwhendataisreadfromtheInputPortregister.Resettingoccursinthereadmodeattheacknowledge(ACK)bitaftertherisingedgeoftheSCLsignal.InterruptsthatoccurduringtheACKclockpulsecanbelost(orbeveryshort)duetotheresettingoftheinterruptduringthispulse.EachchangeoftheI/OsafterresettingisdetectedandistransmittedasaninterruptontheINTpin.FeatureDescriptionReadingfromorwritingtoanotherdevicedoesnotaffecttheinterruptcircuit,andapinconfiguredasanoutputcannotcauseaninterrupt.ChanginganI/OfromanoutputtoaninputmaycauseafalseinterrupttooccurifthestateofthepindoesnotmatchthecontentsoftheInputPortregister.TheINToutputhasanopen-drainstructureandrequirespull-upresistortoDeviceFunctionalPower-OnWhenpower(from0V)isappliedtoVCC,aninternalpower-onresetholdstheTCA9554AinaresetconditionuntilVCChasreachedVPORR.Atthatpoint,theresetconditionisreleasedandtheTCA9554AregistersandSMBus/I2Cstatemachinewillinitializetotheirdefaultstates.Afterthat,VCCmustbeloweredtobelowVPORFandthenbackuptotheoperatingvoltageforapower-onresetcycle.I2CThebidirectionalI2Cbusconsistsoftheserialclock(SCL)andserialdata(SDA)lines.Bothlinesmustbeconnectedtoapositivesupplythroughapull-upresistorwhenconnectedtotheoutputstagesofadevice.Datatransfermaybeinitiatedonlywhenthebusisnotbusy.I2CcommunicationwiththisdeviceisinitiatedbyamastersendingaStartcondition,ahigh-to-lowtransitionontheSDAinput/outputwhiletheSCLinputishigh(seeFigure15).AftertheStartcondition,thedeviceaddressbyteissent,mostsignificantbit(MSB)first,includingthedatadirectionbit(R/W).Afterreceivingthevalidaddressbyte,thisdevicerespondswithanacknowledge(ACK),alowontheSDAinput/outputduringthehighoftheACK-relatedclockpulse.Theaddressinputs(A0–A2)oftheslavedevicemustnotbechangedbetweentheStartandtheStopconditions.OntheI2Cbus,onlyonedatabitistransferredduringeachclockpulse.ThedataontheSDAlinemustremainstableduringthehighpulseoftheclockperiod,aschangesinthedatalineatthistimeareinterpretedascontrolcommands(StartorStop)(seeFigure16).AStopcondition,alow-to-hightransitionontheSDAinput/outputwhiletheSCLinputishigh,issentbythemaster(seeFigure15).AnynumberofdatabytescanbetransferredfromthetransmittertoreceiverbetweentheStartandtheStopconditions.EachbyteofeightbitsisfollowedbyoneACKbit.ThetransmittermustreleasetheSDAlinebeforethereceivercansendanACKbit.ThedevicethatacknowledgesmustpulldowntheSDAlineduringtheACKclockpulsesothattheSDAlineisstablelowduringthehighpulseoftheACK-relatedclockperiod(seeFigure17).Whenaslavereceiverisaddressed,itmustgenerateanACKaftereachbyteisreceived.Similarly,themastermustgenerateanACKaftereachbytethatitreceivesfromtheslavetransmitter.Setupandholdtimesmustbemettoensureproperoperation.Amasterreceiverwillsignalanendofdatatotheslavetransmitterbynotgeneratinganacknowledge(NACK)afterthelastbytehasbeenclockedoutoftheslave.ThisisdonebythemasterreceiverbyholdingtheSDAlinehigh.Inthisevent,thetransmittermustreleasethedatalinetoenablethemastertogenerateaStopcondition.PSPS Figure15.DefinitionofStartandStopProgrammingDataDataLineofDataFigure16.Bit12891289SbySCL

76543210I276543210I2CslaveLHHHPxI/Odata

ClockPulseforRegisterDeviceFigure18showstheaddressbyteofthe0111 Figure18.TCA9554ATable2.AddressI2CBUSSLAVELLL56(decimal),38LLH57(decimal),39LHL58(decimal),3ALHH59(decimal),3BHLL60(decimal),3CHLH61(decimal),3DHHL62(decimal),3EHHH63(decimal),3FThelastbitoftheslaveaddressdefinestheoperation(readorwrite)tobeperformed.Whenitishigh(1),areadisselected,whilealow(0)selectsawriteoperation.ControlRegisterandCommandFollowingthesuccessfulAcknowledgmentoftheaddressbyte,thebusmastersendsacommandbytethatisstoredinthecontrolregisterintheTCA9554A(seeFigure19).Twobitsofthiscommandbytestatetheoperation(readorwrite)andtheinternalregister(input,output,polarityinversionorconfiguration)thatwillbeaffected.ThisregistercanbewrittenorreadthroughtheI2Cbus.Thecommandbyteissentonlyduringawritetransmission.Onceacommandbytehasbeensent,theregisterthatwasaddressedcontinuestobeaccessedbyreadsuntilanewcommandbytehasbeensent.000000Figure19.ControlRegisterBitsTable3.000000CONTROLREGISTERCOMMANDBYTEPOWER-UP00InputReadXXXX01OutputRead/write111110PolarityRead/write000011Read/write1111RegisterTheInputPortregister(register0)reflectstheincominglogiclevelsofthepins,regardlessofwhetherthepinisdefinedasaninputoranoutputbytheConfigurationregister.Itonlyactsonreadoperation.Writestotheseregistershavenoeffect.Thedefaultvalue,X,isdeterminedbytheexternallyappliedlogiclevel.Beforeareadoperation,awritetransmissionissentwiththecommandbytetoindicatetotheI2CdevicethattheInputPortregisterisaccessednext.Table4.Register0(InputPortRegister)XXXXXXXXTheOutputPortregister(register1)showstheoutgoinglogiclevelsofthepinsdefinedasoutputsbytheConfigurationregister.Bitvaluesinthisregisterhavenoeffectonpinsdefinedasinputs.Inturn,readsfromthisregisterreflectthevaluethatisintheflip-flopcontrollingtheoutputselection,nottheactualpinvalue.Table5.Register1(OutputPortRegister)11111111ThePolarityInversionregister(register2)allowspolarityinversionofpinsdefinedasinputsbytheConfigurationregister.Ifabitinthisregisterisset(writtenwith1),thecorrespondingportpinpolarityisinverted.Ifabitinthisregisteriscleared(writtenwitha0),thecorrespondingportpinoriginalpolarityisretained.Table6.Register2(PolarityInversionRegister)00000000TheConfigurationregister(register3)configuresthedirectionsoftheI/Opins.Ifabitinthisregisterissetto1,thecorrespondingportpinisenabledasaninputwithahigh-impedanceoutputdriver.Ifabitinthisregisterisclearedto0,thecorrespondingportpinisenabledasanoutput.Table7.Register3(ConfigurationRegister)11111111BusDataisexchangedbetweenthemasterandTCA9554AthroughwriteandreadDataistransmittedtotheTCA9554Abysendingthedeviceaddressandsettingtheleast-significantbit(LSB)toalogic0(seeFigure18fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregisterreceivesthedatathatfollowsthecommandbyte(seeFigure20andFigure21).Thereisnolimitationonthenumberofdatabytessentinonewritetransmission.

1 34

67

Command

Datato10000000A10000000A1110SPAA0

Figure20.WritetoOutputPort

Data11000000A 1 341000000A

Datato001110S

PAAStart PAA

ACKFrom

ACKFrom

ACKFromDatato

Figure21.WritetoConfigurationorPolarityInversionThebusmasterfirstmustsendtheTCA9554AaddresswiththeLSBsettoalogic0(seeFigure18fordeviceaddress).Thecommandbyteissentaftertheaddressanddetermineswhichregisterisaccessed.Afterarestart,thedeviceaddressissentagainbut,thistime,theLSBissettoalogic1.DatafromtheregisterdefinedbythecommandbytethenissentbytheTCA9554A(seeFigure22andFigure23).Afterarestart,thevalueoftheregisterdefinedbythecommandbytematchestheregisterbeingaccessedwhentherestartoccurred.DataisclockedintotheregisterontherisingedgeoftheACKclockpulse.Thereisnolimitationonthenumberofdatabytesreceivedinonereadtransmission,butwhenthefinalbyteisreceived,thebusmastermustnotacknowledgethedata.

S0

11A2A1A00

AS

11

A2A1A01

NA LastByte Figure22.ReadFrom 1 34 7

DataFrom

DataFrom

S

11A2A1A01

Data

Data

NAReadData

Data Data

Data

Data

ThisfigureassumesthecommandbytehaspreviouslybeenprogrammedwithTransferofdatacanbestoppedatanymomentbyaStopThisfigureeliminatesthecommandbytetransfer,arestart,andslaveaddresscallbetweentheinitialslaveaddresscallandactualdatatransferfromthePport.SeeFigure22forthesedetails.Figure23.ReadFromInputPortApplicationandInformationinthefollowingapplicationssectionsisnotpartoftheTIcomponentspecification,andTIdoesnotwarrantitsaccuracyorcompleteness.TI’scustomersareresponsiblefordeterminingsuitabilityofcomponentsfortheirpurposes.Customersshouldvalidateandtesttheirdesignimplementationtoconfirmsystemfunctionality.ApplicationFigure24showsanapplicationinwhichtheTCA9554AcanbeTypical

10

10

2Subsystem2(e.g.,Subsystem2(e.g.,Subsystem(e.g.,temperature5679A322

(e.g.,CBTSubsystem3(e.g.,Subsystem3(e.g.,alarmsystem)TheSCLandSDApinsmustbetieddirectlytoVCCbecauseifSCLandSDAaretiedtoanauxiliarypowersupplythatcouldbepoweredonwhileVCCispoweredoff,thenthesupplycurrent,ICC,willincreaseasaresult.Deviceaddressisconfiguredas0111000forthisP0,P2,andP3areconfiguredasP1,P4,andP5areconfiguredasP6andP7arenotusedandhaveinternal100-k?pullupresistorstoprotectthemfromFigure24.ApplicationTypicalApplicationDesignMinimizingICCWhenI/OsControlWhentheI/OsareusedtocontrolLEDs,normallytheyareconnectedtoVCCthrougharesistorasshowninFigure24.ForaP-portconfiguredasaninput,ICCincreasesasVIbecomeslowerthanVCC.TheLEDisadiode,withthresholdvoltageVT,andwhenaP-portisconfiguredasaninputtheLEDwillbeoffbutVIisaVTdropbelowVCC.Forbattery-poweredapplications,itisessentialthatthevoltageofP-portscontrollingLEDsisgreaterthanorequaltoVCCwhentheP-portsareconfiguredasinputtominimizecurrentconsumption.Figure25showsahigh-valueresistorinparallelwiththeLED.Figure26showsVCClessthantheLEDsupplyvoltagebyatleastVT.BothofthesemethodsmaintaintheI/OVIatoraboveVCCandpreventsadditionalsupplycurrentconsumptionwhentheP-portisconfiguredasaninputandtheLEDisoff. 100Figure25.High-ValueResistorinParallelWith3.3 5Figure26.DeviceSuppliedbyaLowerTypicalApplicationDetailedDesignThepull-upresistors,RP,fortheSCLandSDAlinesneedtobeselectedappropriatelyandtakeintoconsiderationthetotalcapacitanceofallslavesontheI2Cbus.Theminimumpull-upresistanceisafunctionofVCC,VOL,(max),andIOL:VCCRp(min)

Themaximumpull-upresistanceisafunctionofthemaximumrisetime,tr(