數(shù)字邏輯設(shè)計(jì)及應(yīng)用教學(xué)英文課件：Lec15-Chap 6

1、1,Digital Logic Design and ApplicationLecture #17,Adder ALU,UESTC, Spring 2013,2,5.10 Adder,1. Half Adder and Full Adder,Sum: S = A B Carry: CO = AB,3,5.10 Adder,S = X Y CI,XY,XCI,CO = + +,YCI,= XY + (X+Y)CI,1. Half Adder and Full Adder,4,5.10 Adder,1. Half Adder and Full Adder,S = X Y CI,XY,XCI,CO

2、= + +,YCI,= XY + (X+Y)CI,5,2. Ripple Adder,Speed limited by carry chain,=0,Review of series comparator,Faster adders eliminate or limit carry chain parallel adder, carry lookahead,6,串行比較器,串行加法器,7,3. Iterative Circuit（迭代電路）,Iterative：重復(fù)的, 反復(fù)的, 數(shù)迭代的,cascading outputs,8,4. Carry-Lookahead Adders,Carry-

3、Lookahead(先行進(jìn)位)：第 i 位的進(jìn)位輸出Ci與地位進(jìn)位輸入信號(hào)Ci-1無關(guān)，可由本位輸入信號(hào)Xi和Yi決定。,Ci+1 = (XiYi) + (Xi+Yi) Ci,= Gi + Pi Ci,Si= Xi Yi Ci=Pi Gi Ci=hSi Ci,9,4. Carry-Lookahead Adders,先行進(jìn)位法：第 i 位的進(jìn)位輸入信號(hào)可以由該位以前的各位狀態(tài)決定。,C0 = 0,Ci+1 = Gi + Pi Ci,C0 = 0 C1 = G0+P0C0 C2 = G1+P1C1 = G1+P1(G0+P0C0) = G1+P1G0+ P1P0C0 Cn = Gn+PnCn （P

4、479）,展開為“與-或”式：三級(jí)延遲,MSI Adders 74x283 P480 Fig.6-87,10,74x283 4-bit adder,Uses carry lookahead internally,以消耗更多硬件資源為代價(jià)，獲得更快計(jì)算速度。,Ripple carry between groups,Use 283 to Build a 16-bit adder,組間串行進(jìn)位 加法器,5. Multipliers,How to get a 1-bit multiplier?,12,An AND gate performs a 1-bit multipling,How to get

5、a n-bit multiplier?,Look up table,6. MSI Arithmetic and Logic Units,ALU: perform any one of a number of different arithmetic and logic operations on a pair of b-bit operands.,13,How to build a simplest ALU?,arithmetic,Logic,Truth table,k-map,Logic equation,Logic circuit,1-bit Multiplier,2 input OR gate,F,Structural thinking,4-bit ALU MSI,14,Function outputs,0-arithm