基于ARM和FPGA的高速數(shù)據(jù)采集卡的設(shè)計(jì)與實(shí)現(xiàn)畢業(yè)論文.doc

摘要采集是認(rèn)知的開始、測量的前提、分析的基礎(chǔ)，絕大多數(shù)的電子設(shè)備、儀器都是數(shù)據(jù)采集為基礎(chǔ)。隨著電子技術(shù)和數(shù)字技術(shù)的飛速發(fā)展，信號(hào)的傳輸速度和CPU的處理速度越來越快，因此對數(shù)據(jù)采集和處理的要求也越來越高。由于芯片技術(shù)的限制我國很難在高端的數(shù)據(jù)采集系統(tǒng)中有所作為，一般國內(nèi)的數(shù)據(jù)采集卡都處于中低端產(chǎn)品，多用于中低頻信號(hào)的采集中，很少有符合我們設(shè)計(jì)要求的高速采集系統(tǒng)。課題中的高速數(shù)據(jù)采集卡是研究高性能分析儀器的一部分，它與一般的數(shù)據(jù)采集卡存在區(qū)別，主要區(qū)別在于我們的系統(tǒng)對數(shù)據(jù)輸出的要求不強(qiáng)，系統(tǒng)可以自成系統(tǒng)，有一定的數(shù)據(jù)處理和分析能力。本設(shè)計(jì)采用AD轉(zhuǎn)換器+FPGA芯片+ARM處理器的結(jié)構(gòu)，實(shí)現(xiàn)了采樣率為250M的數(shù)據(jù)采集卡。論文從宏觀和微觀兩個(gè)方面來分析數(shù)據(jù)采集卡的各個(gè)組成部分。從宏觀上分析了采集系統(tǒng)中各個(gè)芯片間的數(shù)據(jù)流向、速度匹配和具體通信方式的選擇等問題。使用乒乓機(jī)制降低了數(shù)據(jù)處理的速度，來降低FPGA中的預(yù)處理難度，使FPGA處理時(shí)序余量更加充裕。在ARM與FPGA通信方式上使用DMA傳輸，大大提高了數(shù)據(jù)傳輸?shù)乃俾剩⒔夥帕撕蠖说腁RM處理器。設(shè)計(jì)從宏觀上優(yōu)化數(shù)據(jù)傳輸?shù)男剩浞职l(fā)揮器件的性能，并提出了一些改進(jìn)系統(tǒng)性能的方案。從微觀實(shí)現(xiàn)上，數(shù)據(jù)是從前端數(shù)據(jù)調(diào)理電路進(jìn)入AD轉(zhuǎn)換器，再由FPGA采集AD轉(zhuǎn)換器輸出的數(shù)據(jù)，后經(jīng)過數(shù)據(jù)的觸發(fā)、成幀等預(yù)處理，預(yù)處理后的數(shù)據(jù)再傳輸給后端的ARM處理器，最后由ARM處理器送給LCD顯示。微觀實(shí)現(xiàn)的過程中遇到了很多問題，主要是在AD數(shù)據(jù)的采集和采集數(shù)據(jù)的傳輸上。在后期的系統(tǒng)調(diào)試中遇到了采集數(shù)據(jù)錯(cuò)位、ARM與FPGA通信效率低下，還有FPGA中預(yù)處理時(shí)序緊張等問題，通過硬件軟件部分的修改，問題都得到一定程度的解決。在整個(gè)數(shù)據(jù)采集卡的設(shè)計(jì)過程中還遇到高速PCB設(shè)計(jì)、硬件設(shè)計(jì)可靠性、設(shè)計(jì)冗余性和可擴(kuò)展性等問題，這些都是硬件設(shè)計(jì)中的需要考慮和重視的問題，在論文的最后一章有詳細(xì)論述。關(guān)鍵詞：高速數(shù)據(jù)采集觸發(fā)高速PCB設(shè)計(jì)AbstractDateacquisitionisthepremiseofmeasure,thefoundationofanalysisandthebeginningofcognition.Mostprecisedeviceisbasedonthedateacquisition.Withthedevelopmentoftheelectronicanddigitaltechnology,thespeedofdatetransmissionandthecalculationofCPUarefasterandfaster；thereforetherequirementsofdataacquisitionandprocessingaremoreseverethanbefore.Itishardforustomakeabrilliantsuccessintheareaofhigh-enddataacquisitionduetotherestraintofthetechnologyofchip.Atpresentthedataacquisitioncardinourcountryarealmostlow-endproductswhicharealwaysusedtodealwithmedianfrequencieslowfrequencies.Andthesystemsofacquisitionseldomarelinewiththedemandingofourdesign.Inthispaper,high-speeddataacquisitioncardisapartofhighperformanceanalyticalinstruments.Thedifferencesbetweenthiskindofcardsandtheothersarethattheyarenotrigidtotheoutputofsystemandhavetheabilityofdataanalyzingandprocessing.Wesuccessfullydesignasystemof250MsamplingfrequenciesbasedonthestructureofA/D,FPGAandARM.ThispaperanalyzesthesystemfromMacro-andmicrorespect.Fromthemacropointofviewitanalyzesdataflowing,speedmatchingandtheselectionofspecificmeansofcommunicationofacquisitionsystemandsoon.Weadaptping-pongmechanismtoreducethespeedofanalyzingdataandpre-difficultofFPGAwhichleadtotheeaseofprocessingTimingMarginofFPGA.DMAtransferisusedascommunicationbetweenARMandFPGAwhichimprovedatatransmissionrates,andliberatetheback-endARMprocessor.Fromthemicropointofview,dataenterintotheA/Dconverterfromthefront-endconditioningcircuitry,FPGAcollectingdataontheoutputofA/Dconverterandgothroughthepre-operationoftriggeringandframingofdata.Aftertheseoperations,dataaretransmittedtotheback-endoftheARMprocessorandthendisplayontheLCD.AlotofdifficultexitedinthesuccessfuloperationinthemicrorespectwhichismainlyaboutA/Ddatacollectionandtheoftransmissiondata.Inthelatterpartofthesystemweencounterthedislocationdatacollection,theinefficiencyofARMandFPGAcommunicationandthetensionoftiminginthepre-operationofFPGA.Alloftheseissueshavebeensettledbytherevisingofhardwareandsoftware.Therearealsosomeproblemsencounteredinthedesignprocessofdataacquisitioncard,suchasthedesignofHigh-speedPCB,thereliabilityofhardwaredesignreliability,redundancyandscalabilityofthesystem.Allthesolutionsoftheseproblemsareillustratedinthelastpartofthispaper.Keyword：High-speedDataAcquisitionTriggeringHigh-speedPCB目錄摘要.IAbstract.II第一章緒論.11.1高速數(shù)據(jù)采集現(xiàn)狀.11.2數(shù)據(jù)采集卡在測試儀器中的應(yīng)用.11.3數(shù)據(jù)采集卡主要的性能指標(biāo).21.4本文主要研究工作和難點(diǎn).2第二章系統(tǒng)設(shè)計(jì)方案和主要器件選型.42.1系統(tǒng)設(shè)計(jì)方案.42.2ADC芯片選型.42.3DA芯片選型.52.4FPGA芯片選型.62.5主控CPU選型.9第三章數(shù)據(jù)采集與觸發(fā)電路設(shè)計(jì).113.1前端采集電路設(shè)計(jì).113.2觸發(fā)電路與觸發(fā)控制.133.3采集中的問題和解決方法.163.4SDRAM控制器設(shè)計(jì).20第四章各芯片間的數(shù)據(jù)傳輸與