NRF24L01無線通訊8051驅(qū)動(dòng)程序.doc

/=/ 工程名稱: NRF24L01無線通訊8051驅(qū)動(dòng)程序 / 硬件連接: NRF24L01無線通訊模塊和8051單片機(jī) /=嘉興學(xué)院電子創(chuàng)新實(shí)驗(yàn)室2012年=#include #include typedef unsigned char uchar;typedef unsigned int uint;/*IO端口定義*sbit MISO=P20;sbit MOSI=P21;sbitSCK =P22;sbitCE =P23;sbitCSN=P24;sbitIRQ=P22;/*定義待發(fā)數(shù)據(jù)寬度和內(nèi)容*#define TX_PLOAD_WIDTH 1 / 1 uchar TX payload#define RX_PLOAD_WIDTH 1 / 1 uchar TX payloaduchar TxBuf1=0xaa;uchar RxBuf1;/*定義NRF24L01通訊地址寬度和內(nèi)容*#define TX_ADR_WIDTH 5 / 5 uchar TX address width#define RX_ADR_WIDTH 5 / 5 uchar RX address widthuchar const TX_ADDRESSTX_ADR_WIDTH= 0x34,0x43,0x10,0x10,0x01;/本地地址uchar const RX_ADDRESSRX_ADR_WIDTH= 0x34,0x43,0x10,0x10,0x01;/接收端地址/*NRF24L01寄存器指令*#define READ_REG 0x00 / 讀寄存器指令#define WRITE_REG 0x20 / 寫寄存器指令#define RD_RX_PLOAD 0x61 / 讀取接收數(shù)據(jù)指令#define WR_TX_PLOAD 0xA0 / 寫入待發(fā)數(shù)據(jù)指令#define FLUSH_TX 0xE1 / 沖洗發(fā)送 FIFO指令#define FLUSH_RX 0xE2 / 沖洗接收 FIFO指令#define REUSE_TX_PL 0xE3 / 定義重復(fù)裝載數(shù)據(jù)指令#define NOP 0xFF / 保留/*SPI(nRF24L01)寄存器地址*#define CONFIG 0x00 / 配置收發(fā)狀態(tài)，CRC校驗(yàn)?zāi)Ｊ揭约笆瞻l(fā)狀態(tài)響應(yīng)方式#define EN_AA 0x01 / 自動(dòng)應(yīng)答功能設(shè)置#define EN_RXADDR 0x02 / 可用信道設(shè)置#define SETUP_AW 0x03 / 收發(fā)地址寬度設(shè)置#define SETUP_RETR 0x04 / 自動(dòng)重發(fā)功能設(shè)置#define RF_CH 0x05 / 工作頻率設(shè)置#define RF_SETUP 0x06 / 發(fā)射速率、功耗功能設(shè)置#define STATUS 0x07 / 狀態(tài)寄存器#define OBSERVE_TX 0x08 / 發(fā)送監(jiān)測(cè)功能#define CD 0x09 / 地址檢測(cè) #define RX_ADDR_P0 0x0A / 頻道0接收數(shù)據(jù)地址#define RX_ADDR_P1 0x0B / 頻道1接收數(shù)據(jù)地址#define RX_ADDR_P2 0x0C / 頻道2接收數(shù)據(jù)地址#define RX_ADDR_P3 0x0D / 頻道3接收數(shù)據(jù)地址#define RX_ADDR_P4 0x0E / 頻道4接收數(shù)據(jù)地址#define RX_ADDR_P5 0x0F / 頻道5接收數(shù)據(jù)地址#define TX_ADDR 0x10 / 本地地址寄存器#define RX_PW_P0 0x11 / 接收頻道0接收數(shù)據(jù)長(zhǎng)度#define RX_PW_P1 0x12 / 接收頻道0接收數(shù)據(jù)長(zhǎng)度#define RX_PW_P2 0x13 / 接收頻道0接收數(shù)據(jù)長(zhǎng)度#define RX_PW_P3 0x14 / 接收頻道0接收數(shù)據(jù)長(zhǎng)度#define RX_PW_P4 0x15 / 接收頻道0接收數(shù)據(jù)長(zhǎng)度#define RX_PW_P5 0x16 / 接收頻道0接收數(shù)據(jù)長(zhǎng)度#define FIFO_STATUS 0x17 / FIFO棧入棧出狀態(tài)寄存器設(shè)置/*void Delay(uint s);/長(zhǎng)延時(shí)void inerDelay_us(uchar n);/延時(shí)void init_NRF24L01(void);/初始化uchar SPI_RW(uchar uchar_data);/SPI讀寫數(shù)據(jù)uchar SPI_Read(uchar reg);/SPI讀寄存器void SPI_RW_Reg(uchar reg, uchar value);/SPI寫寄存器void SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars);/SPI讀多字節(jié)數(shù)據(jù)void SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars);/SPI寫多字節(jié)數(shù)據(jù)void SetRX_Mode(void);/數(shù)據(jù)接收設(shè)置void SetTX_Mode(void);/數(shù)據(jù)發(fā)送設(shè)置void nRF24L01_RxPacket(uchar* rx_buf);/接收數(shù)據(jù)函數(shù)void nRF24L01_TxPacket(uchar * tx_buf);/發(fā)送數(shù)據(jù)函數(shù)/*uchar bdata sta; /狀態(tài)標(biāo)志sbitRX_DR =sta6;sbitTX_DS =sta5;sbitMAX_RT =sta4;/*長(zhǎng)延時(shí)*void Delay(uint s)uint i,j;for(i=0; is; i+)for(j=0; j0;n-)_nop_();/*/*NRF24L01初始化/*void init_NRF24L01(void) inerDelay_us(100); CE=0; / StandBy I模式 CSN=1; / Spi disable SCK=0; / Spi clock line init lowSPI_RW_Reg(WRITE_REG + CONFIG, 0x5e); /IRQ發(fā)送完成中斷響應(yīng)，主發(fā)送SPI_RW_Reg(WRITE_REG + EN_AA, 0x00); /允許頻道0自動(dòng)應(yīng)答SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); /允許接收地址只有頻道0 /SPI_RW_Reg(WRITE_REG + SETUP_AW, 0x01); /設(shè)置接收地址長(zhǎng)度，本次設(shè)置為3字節(jié)/SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x00);/設(shè)置禁止自動(dòng)重發(fā)SPI_RW_Reg(WRITE_REG + RF_CH, 0x02); /設(shè)置信道工作頻率，收發(fā)必須一致SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x0f); /設(shè)置發(fā)射速率為2MHZ，發(fā)射功率為最大值0dBSPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); /寫接收端地址SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); /寫本地地址SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); /設(shè)置接收數(shù)據(jù)長(zhǎng)度，本次設(shè)置為1字節(jié)inerDelay_us(150);/*/*函數(shù)：uint SPI_RW(uint uchar_data)/*功能：NRF24L01的SPI讀寫數(shù)據(jù)/*uchar SPI_RW(uchar uchar_data) uchar bit_ctr; for(bit_ctr=0;bit_ctr8;bit_ctr+) / output 8-bit MOSI = (uchar_data & 0x80); / output uchar_data, MSB to MOSIuchar_data = (uchar_data 1); / shift next bit into MSB.SCK = 1; / Set SCK high.uchar_data |= MISO; / capture current MISO bitSCK = 0; / .then set SCK low again return(uchar_data); / return read uchar_data/*/*函數(shù)：uchar SPI_Read(uchar reg)/*功能：NRF24L01的SPI讀寄存器and clear/*uchar SPI_Read(uchar reg)uchar reg_val;CSN = 0; / CSN low, initialize SPI communication.SPI_RW(reg); / Select register to read from.reg_val = SPI_RW(0); / .then read registervalueCSN = 1; / CSN high, terminate SPI communicationreturn(reg_val); / return register value/*/*函數(shù)：uint SPI_RW_Reg(uchar reg, uchar value)/*功能：NRF24L01的SPI寫寄存器函數(shù)，返回status/*void SPI_RW_Reg(uchar reg, uchar value)CSN = 0; / CSN low, init SPI transaction SPI_RW(reg); / select registerSPI_RW(value); / .and write value to it.CSN = 1; / CSN high again/*/*函數(shù)：uint SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars)/*功能: 用于讀數(shù)據(jù)，reg：指令+為寄存器地址，pBuf：為待讀出數(shù)據(jù)地址，uchars：讀出數(shù)據(jù)的個(gè)數(shù)/*void SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars)uchar uchar_ctr;CSN = 0; / Set CSN low, init SPI tranactionSPI_RW(reg); / Select register to write to and read status ucharfor(uchar_ctr=0;uchar_ctruchars;uchar_ctr+)pBufuchar_ctr = SPI_RW(0); CSN = 1; /*/*函數(shù)：uint SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars)/*功能: 用于寫數(shù)據(jù)，reg：為指令+寄存器地址，pBuf：為待寫入數(shù)據(jù)地址，uchars：寫入數(shù)據(jù)的個(gè)數(shù)/*void SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars)uchar uchar_ctr;CSN = 0; /SPI使能 SPI_RW(reg); for(uchar_ctr=0; uchar_ctruchars; uchar_ctr+) SPI_RW(*pBuf+);CSN = 1; /關(guān)閉SPI/*/*函數(shù)：void SetRX_Mode(void)/*功能：數(shù)據(jù)接收配置 /*void SetRX_Mode(void)CE=0;SPI_RW_Reg(WRITE_REG + CONFIG, 0x3f); / IRQ接收完成中斷響應(yīng)，主接收CE = 1; inerDelay_us(130);/*/*函數(shù)：void SetTX_Mode(void)/*功能：數(shù)據(jù)發(fā)送配置 /*void SetTX_Mode(void)CE=0;SPI_RW_Reg(WRITE_REG + CONFIG, 0x7e); / IRQ禁止中斷響應(yīng)，主發(fā)送/*/*函數(shù)：void nRF24L01_RxPacket(unsigned char* rx_buf)/*功能：讀取RX_FIFO數(shù)據(jù)，然后存入自定義數(shù)組中/*void nRF24L01_RxPacket(uchar* rx_buf)SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);/ read receive payload from RX_FIFO bufferCE=0; SPI_RW_Reg(WRITE_REG+STATUS,0x70); /接收到數(shù)據(jù)后RX_DR置高為1，通過寫1來清楚中斷標(biāo)志SPI_RW(FLUSH_RX); / 沖洗接收 FIFO指令 CE=1;inerDelay_us(130);/*/*函數(shù)：void nRF24L01_TxPacket(