基于FPGA的VHDL語言m序列生成詳解+源碼.doc

說明可控m序列產(chǎn)生器我分成四個小模塊來做，M，M1，M2，M3分別對應(yīng)為：m序列產(chǎn)生器、控制器、碼長選擇器、碼速率選擇器。一、M: m序列產(chǎn)生器這是該設(shè)計的核心部分，原理就是設(shè)計一個通用m序列產(chǎn)生子單元，然后由外部選擇器來寫入碼型，碼長等參數(shù)，加以循環(huán)可連接成任意長度的m序列產(chǎn)生器，其子單元結(jié)構(gòu)如下：C(N)A(N)Q(N+1)C(N-1)Q(N)B(N)D+CP如上圖，若N=15，就有15個這樣的子單元首尾相接。注意：開頭和結(jié)尾的兩個子單元會有所不同，因為首單元需要輸入初值，尾單元要進行直通反饋，在程序里請多留意。圖中，主要部件是一個D觸發(fā)器，Q(N+1)為上一級輸出；Q(N)既是本級輸出；CP為選擇后的時鐘脈沖；B(N)為本級參數(shù)選擇控制；A(N)受控于B(N),決定本級輸出Q(N)是否反饋（B(N)為1時反饋）； C（N）為本級反饋；C（N-1）為下一級反饋。具體原理參看m序列組成結(jié)構(gòu)。此外，本程序還加入了EN(發(fā)送控制)、RN(首單元置數(shù))、SEL1(碼長選擇，即N的選擇，N=2-15)、SEL2(碼型選擇，即正逆碼選擇)四個控制端，可滿足設(shè)計要求。OP為碼輸出端。二、M1：控制器控制器主要是將外部的序列發(fā)送控制信號STA轉(zhuǎn)換為EN和RN兩個控制信號。其中，EN與STA的波形基本一致，只是它與CP進行了同步處理；RN在EN為1的頭一個脈沖周期里置高電平，以達到為序列發(fā)生器的首端置數(shù)的目的。如果不清楚的話可以看一下它的模擬波形。（注意：STA要采用自鎖定開關(guān)，高電平有效）三、M2：碼長選擇序列的碼長選擇既是N值的選擇，碼長=2*N-1。核心就是一個計數(shù)器，可從2計到15。按一次PUSH就可以自動加一（注意：按鍵建議采用自彈跳按鍵，如過需要軟件清除按鍵震顫的話，我再做發(fā)給你），沒有0，1兩個狀態(tài)。如果需要的話還可以擴展7段數(shù)碼管的接口，以顯示N值。四、M3：碼速率選擇器碼的傳輸速率是靠CP來控制的，CP的頻率就等于碼元速率。這段程序包含一個倍頻器，一個5分頻的分頻器，可把5MHZ的脈沖源CLK擴展成1MHZ和10MHZ。FSEL1、FSLE2、FSEL3分別在選擇1、5、10MHZ時為高電平，其余兩個為低，建議采用3選1單刀單擲開關(guān)。M1-LIBRARY IEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCTRLISPORT(CP,STA:IN STD_LOGIC;EN,RN:OUT STD_LOGIC);ENDCTRL;ARCHITECTURE a OF CTRL ISSIGNALQ1,Q2:STD_LOGIC;BEGINPROCESS(CP)BEGINIF CPevent AND CP=1 THENQ2=Q1;Q1=STA;END IF;END PROCESS;EN=Q1;RN=Q1 AND NOT Q2;END a;M2-LIBRARY IEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCOUNTER ISPORT(PUSH,EN,RST:IN STD_LOGIC;SEL1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);ENDCOUNTER;ARCHITECTURE a OF COUNTER ISSIGNALB,C:STD_LOGIC;SIGNALQN:STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS(PUSH,C)BEGINIF EN=0 THENIF C=1 THENQN=”0010”;ELSEIF PUSHEVENT AND PUSH=1 THENQN=QN+1;END IF;ELSEQN=QN;END IF;END PROCESS;B=1 WHEN QN=”0000” ELSE 0;C=B OR RST;SEL1=QN;END a;M3-LIBRARY IEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYFP ISPORT(CLK,FSEL1,FSEL2,FSEL3:IN STD_LOGIC;CP:OUT STD_LOGIC);ENDFP;ARCHITECTURE a OF FP ISSIGNALQ1,Q2,Q3,RST: STD_LOGIC; SIGNALM1,M5,M10: STD_LOGIC;SIGNALQN: STD_LOGIC_VECTOR(2 DOWNTO 0);BEGINBP1 : BLOCKBEGINPROCESS(CLK,Q1)BEGINIF Q1=1 THENQ1=0ELSEIF CLKEVENT AND CLK=1 THENQ1=1;END IF;END PROCESS;END BLOCK BP1;BP2 : BLOCKBEGINPROCESS(CLK,Q2)BEGINIF Q2=1 THENQ2=0ELSEIF CLKEVENT AND CLK=0 THENQ2=1;END IF;END PROCESS;END BLOCK BP2;FP : BLOCKBEGINPROCESS(CLK,RST)BEGINIF RST=1 THENQN=”000”;ELSEIF CLKEVENT AND CLK=1 THENQN=QN+1;END IF;END PROCESS;END BLOCK FP;Q3=Q1 OR Q2;RST=1 WHEN QN=”101” ELSE 0;M1=QN(2) AND FSEL1;M2=CLK AND FSEL2;M3=Q3 AND FSEL3;CP=M1 OR M2 OR M3;END a;M-LIBRARY IEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYPN1ISPORT(CP,SEL2,EN,RN:IN STD_LOGIC;SEL1:IN STD_LOGIC_VECTOR(3 DOWNTO 0);OP:OUT STD_LOGIC);ENDPN1;ARCHITECTURE a OF PN1 ISSIGNALQ, A,B,C :STD_LOGIC_VECTOR(14 DOWNTO 0);SIGNALSEL:STD_LOGIC_VECTOR(4 DOWNTO 0);BEGINSEL=SEL1&SEL2;PROCESS (CP,SEL)BEGINIF CPevent AND CP=1 THENIF EN=0 THENQ=000000000000000;OP=Q(0);ELSEQ(14)=C(14) OR RN;BC(0)=Q(0);B(1)=1;FOR I IN 1 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(0)=Q(0);B(14)=1;FOR I IN 1 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(1)=Q(1);B(2)=1;B(7)=1;B(11)=1;FOR I IN 2 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(1)=Q(1);B(5)=1;B(9) =1;B(14) =1;FOR I IN 2 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(2) =Q(2);B(3) =1;B(5) =1;B(6) =1;FOR I IN 3 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(2) =Q(2);B(11) =1;B(12) =1;B(14) =1;FOR I IN 3 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(3) =Q(3);B(4) =1;B(7) =1;B(9) =1;FOR I IN 4 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(3) =Q(3);B(9) =1;B(11) =1;B(14) =1;FOR I IN 4 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(4) =Q(4);B(6) =1; FOR I IN 5 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(4) =Q(4);B(13) =1; FOR I IN 5 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(5) =Q(5);B(8) =1; FOR I IN 6 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(5) =Q(5);B(12) =1; FOR I IN 6 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(6) =Q(6);B(10) =1; FOR I IN 7 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(6) =Q(6);B(11) =1; FOR I IN 7 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(7) =Q(7);B(9) =1;B(10) =1;B(11) =1;FOR I IN 8 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(7) =Q(7);B(11) =1;B(12) =1;B(13) =1; FOR I IN 8 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(8) =Q(8);B(11) =1; FOR I IN 9 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(8) =Q(8);B(12) =1;FOR I IN 9 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(9) =Q(9);B(10) =1;FOR I IN 10 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(9) =Q(9);B(14) =1; FOR I IN 10 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(10) =Q(10);B(12) =1; FOR I IN 11 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(10) =Q(10);B(13) =1; FOR I IN 11 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(11) =Q(11);B(12) =1; FOR I IN 12 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(11) =Q(11);B(14) =1;FOR I IN 12 TO 14 LOOPQ(I-1)=Q(I);A(I)=Q(I) AND B(I);C(I)=C(I-1) XOR A(I);END LOOP;OPC(12) =Q(12);B(13) =1; FOR I IN 13 TO 14 LOOPQ(I-