VHDL例程代碼

【例3-1】 2選1多路選擇器程序。（P31）LIBRARY IEEE; -IEEE庫使用說明語句USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 IS -實(shí)體說明部分PORT(a,b : IN STD_LOGIC;s: IN STD_LOGIC;y: OUT STD_LOGIC);END ENTITY mux21;ARCHITECTURE mux21a OF mux21 IS -結(jié)構(gòu)體說明部分BEGINPROCESS(a,b,s)BEGINIF s=0 THEN y=a;ELSEy=b;END IF;END PROCESS;END ARCHITECTURE mux21a;【例3-2】 有類屬說明的2輸入與非門的實(shí)體描述。（P33）ENTITY nand2 IS GENERIC ( t_rise : TIME := 2ns ;t_fall : TIME := 1ns ) PORT( a: IN BIT; b : IN BIT; s : OUT BIT);END ENTITY nand2;【例3-3】 n輸入與非門的實(shí)體描述：（P33）ENTITY nand_n IS GENERIC ( n : INTEGER ) ; PORT( a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); s : OUT STD_LOGIC );END ENTITY nand_n;例3-4】 半加器的完整VHDL描述，其中x、y為加數(shù)與被加數(shù)，s為和信號，c為進(jìn)位信號。（P36）ENTITY half_adder IS PORT( x,y : IN BIT; s: IN BIT; c: OUT BIT);END ENTITY half_adder;ARCHITECTURE dataflow OF half_adder IS BEGIN s = x XOR y; c = x AND y;END ARCHITECTURE dataflow;【例3-5】 2選1多路選擇器的行為描述程序。（P37）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 ISPORT(a,b : IN STD_LOGIC;s: IN STD_LOGIC;y: OUT STD_LOGIC );END ENTITY mux21;ARCHITECTURE behav OF mux21 ISBEGIN PROCESS(a,b,s)BEGINIF s=0 THEN y=a;ELSEy=b;END IF;END PROCESS;END ARCHITECTURE behav;【例3-6】 2選1多路選擇器數(shù)據(jù)流描述程序。（P36）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 IS PORT(a,b : IN STD_LOGIC;s: IN STD_LOGIC;y: OUT STD_LOGIC);END ENTITY mux21;ARCHITECTURE dataflow OF mux21 IS BEGINy=(a AND (NOT s) OR (b AND s);END ARCHITECTURE dataflow;【例3-7】 2選1多路選擇器結(jié)構(gòu)描述程序。（P37）LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY and21 IS PORT(i0,i1 : IN STD_LOGIC;q: OUT STD_LOGIC );END ENTITY and21;ARCHITECTURE one OF and21 IS BEGIN q=i0 AND i1; END ARCHITECTURE one;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY or21 IS PORT(i0,i1 : IN STD_LOGIC;q: OUT STD_LOGIC );END ENTITY or21;ARCHITECTURE one OF or21 IS BEGIN q=i0 OR i1; END ARCHITECTURE one;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY inv21 IS PORT(i0 : IN STD_LOGIC;q: OUT STD_LOGIC );END ENTITY inv21;ARCHITECTURE one OF inv21 IS BEGIN q= (NOT i0); END ARCHITECTURE one;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux21 IS PORT(a,b : IN STD_LOGIC;s: IN STD_LOGIC;y: OUT STD_LOGIC );END ENTITY mux21;ARCHITECTURE struct OF mux21 IS COMPONENT and21PORT (i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT;COMPONENT or21PORT (i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC);END COMPONENT;COMPONENT inv21PORT (i0: IN STD_LOGIC; q: OUT STD_LOGIC); END COMPONENT;SIGNAL tmp1,tmp2,tmp3:STD_LOGIC;BEGIN u1: and21 PORT MAP (b, s,tmp1); u2: inv21 PORT MAP(s,tmp2);u3: and21 PORT MAP (a,tmp2,tmp3); u4: or21 PORT MAP(tmp1,tmp3,y);END ARCHITECTURE struct;【例3-8】 半加器的混合描述程序。（P37）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xor21 IS PORT(i0,i1:IN STD_LOGIC; q: OUT STD_LOGIC);END ENTITY xor21;ARCHITECTURE behav OF xor21 IS BEGIN q=i0 XOR i1; END ARCHITECTURE behav;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY half_adder IS PORT(a,b:IN STD_LOGIC; c,s: OUT STD_LOGIC);END ENTITY half_adder;ARCHITECTURE mix OF half_adder IS COMPONENT xor21 IS PORT(i0,i1:IN STD_LOGIC; q:OUT STD_LOGIC); END COMPONENT; BEGIN c = a AND b; u1: xor21 PORT MAP(a,b,s); END ARCHITECTURE mix;【例3-9】 打開一個(gè)字符文件，讀出文件中的內(nèi)容并關(guān)閉文件。（P51）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY readfile ISPORT( cs:IN STD_LOGIC; c: OUT CHARACTER);END ENTITY readfile;ARCHITECTURE read1 OF readfile ISBEGINPROCESS(cs)TYPE char_file IS FILE OF CHARACTER;FILE cfile : char_file;VARIABLE i : INTEGER :=0;BEGINIF(cs=1) THEN FILE_OPEN(cfile,f:/leifr/testfile.asc,READ_MODE); WHILE NOT ENDFILE(cfile) LOOP READ(cfile,c); i := i+1; END LOOP; FILE_CLOSE(cfile);ELSEc= - ;END IF;END PROCESS; END ARCHITECTURE read1;【例4-1】 WAIT語句示例程序。（P65）cwait1 ： PROCESS BEGINy = ( a AND b ) OR ( m XOR t ) ;z = c NAND d ; WAIT ; - 無限等待 END PROCESS cwait1 ;【例4-2】 WAIT FOR語句示例程序。（65）cwait2 ： PROCESS BEGIN y = ( a AND b ) OR ( m XOR t ) ; z = c NAND d ; WAIT FOR 10 * ( ct1 + ct2 ) ; - 等待由該表達(dá)式計(jì)算的時(shí)間 END PROCESS cwait2 ;【例4-3】 WAIT ON語句示例程序（二選一選擇器）。（P66）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux2_1 ISPORT( data0, data1 : IN STD_LOGIC ; sel : IN STD_LOGIC ; q : OUT STD_LOGIC ) ;END mux2_1 ;ARCHITECTURE behavioral OF mux2_1 ISSIGNAL temp1, temp2, temp3 : STD_LOGIC ;BEGINcwait3 ： PROCESS BEGIN temp1 = data0 AND sel ; temp2 = data1 AND ( NOT sel ) ; temp3 = temp1 OR temp2 ; q = temp3 ; WAIT ON data0, data1, q ; END PROCESS cwait3 ;END behavioral ;【例4-4】 WAIT ON語句和PROCESS語句中所使用的敏感信號列表的對比。（P67）ARCHITECTURE behavioral OF mux2_1 ISSIGNAL temp1, temp2, temp3 : STD_LOGIC ;BEGINcwait4 ： PROCESS ( data0, data1, q ) BEGIN temp1 = data0 AND sel ; temp2 = data1 AND ( NOT sel ) ; temp3 = temp1 OR temp2 ; q = 20 ) ; - 該表達(dá)式是布爾表達(dá)式 END PROCESS cwait5 ;END behavioral ;【例4-6】 多條件WAIT語句的示例程序。（P68）cwait6 ： PROCESS BEGIN M - 多條件WAIT語句 WAIT ON data0, data1,q UNTIL(temp + 5 ) = 20) FOR 34 ns ; END PROCESS cwait6 ;【例4-7】 信號代入語句示例程序。（P68）ARCHITECTURE behavioral OF example_dairu ISSIGNAL a, b, c, d,e, f : STD_LOGIC ;SIGNAL temp0, temp1, temp2, temp3, temp4, temp5 : STD_LOGIC ;BEGINcdairu ： PROCESS BEGIN temp0 = a NAND b ; - 與非 temp1 = c NOR d ; - 或非 temp2 = e XOR f AFTER 5 ns ; - 異或門延遲 temp3 = ( a NAND b ) NOR ( c NAND d ) ; temp4 = ( c OR d ) NAND ( e OR f ) ; temp5 = a XOR b XOR c XOR d XOR e XOR f ; END PROCESS cdairu ;END behavioral ;【例4-8】 變量賦值語句示例程序。（P69）ARCHITECTURE behavioral OF example_fuzhi ISCONSTANT cvolt : REAL : = 3.3 ; - 定義常數(shù)CONSTANT ccurrent : REAL : = 4.0 ;VARIABLE temp0, temp1 : REAL ; - 定義變量VARIABLE temp2, temp3 : INTEGER RANGE 0 TO 255 : = 10 ;VARIABLE temp4 : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ;VARIABLE temp5 : STD_LOGIC ;SIGNAL a : STD_LOGIC ; - 定義信號SIGNAL b : REAL ;SIGNAL c : INTEGER ;SIGNAL d : STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ;BEGINcfuzhi ： PROCESS BEGIN temp0 : = cvolt ; - 變量直接賦值 temp1 : = ( cvolt + 1.8 ) * ccurrent ; - 變量表達(dá)式賦值 temp2 : = c + 78 ; temp3 : = c / 5 ; - 此時(shí)c必須是5的倍數(shù) temp4 : = d ; temp5 : = temp4 ( 2 ) ; END PROCESS cfuzhi ;END behavioral ;【例4-9】 變量賦值和信號量代入的對比示例程序。（P69）ARCHITECTURE behavioral OF example_duibi ISSIGNAL d0, d1, d2, d3 : STD_LOGIC ; - 定義信號SIGNAL q0, q1 : STD_LOGIC ;BEGINcduibi_1 ：PROCESS (d0, d1, d2, d3 ) BEGIN d2 = d0 ; - 信號量代入 q0 = d2 OR d3 ; d2 = d1 ; - 信號量代入 q1 = d2 OR d3 ; END PROCESS cduibi_1 ;cduibi_2 ： PROCESS (d0, d1, d3 ) VARIABLE m2 : STD_LOGIC ; BEGIN m2 : = d0 ; - 變量賦值 q0 = m2 OR d3 ; m2 : = d1 ; - 變量賦值 q1 = m2 OR d3 ; END PROCESS cduibi_2 ;END behavioral ;進(jìn)程cduibi_1的運(yùn)行結(jié)果：q0 = d1 OR d3 并且 q1 = d1 OR d3進(jìn)程cduibi_2的運(yùn)行結(jié)果：q0 = d0 OR d3 而 q1 = d1 OR d3【例4-10】 采用單IF語句來描述D觸發(fā)器的示例程序。（P71）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY cdff1 ISPORT( d : IN STD_LOGIC ; clk : IN STD_LOGIC ; q : OUT STD_LOGIC ; qnot : OUT STD_LOGIC ) ;END cdff1 ;ARCHITECTURE dataflow OF cdff1 ISBEGINcdff_example : PROCESS ( clk ) BEGIN IF ( clkEVENT AND clk = 1 ) THEN - 單IF語句 q = d ; qnot = NOT d ; END IF ; END PROCESS cdff_example ;END dataflow ;【例4-11】 采用二選擇的IF語句來描述二選一選擇器的示例程序。（P72）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux2_2 ISPORT( a0, a1 : IN BIT ; sel : IN BIT ; q : OUT BIT ) ;END mux2_2 ;ARCHITECTURE rtl OF mux2_2 ISBEGINcmux2_2 : PROCESS (a0, a1, sel ) BEGIN IF ( sel = 1 ) THEN - 二選擇的IF語句 q = a0 ; ELSE q = a1 ; END IF ; END PROCESS cmux2_2 ;END rtl ;【例4-12】 采用多選擇的IF語句來描述4選1選擇電路的示例程序。（P73）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux4_1 ISPORT( a0, a1, a2, a3 : IN STD_LOGIC ; sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; q : OUT STD_LOGIC ) ;END mux4_1 ;ARCHITECTURE rtl OF mux4_1 ISBEGINcmux4_1 : PROCESS (a0, a1, a2, a3, sel ) BEGIN IF ( sel = 00 ) THEN - 多選擇的IF語句 q = a0 ; ELSIF ( sel = 01 ) THEN q = a1 ; ELSIF ( sel = 10 ) THEN q = a2 ; ELSE q = a3 ; END IF ; END PROCESS cmux4_1 ;END rtl ;【例4-13】 采用IF語句嵌套結(jié)構(gòu)的帶復(fù)位端的四選一選擇器的示例程序。（P74）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux4_2 ISPORT( cdata : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; creset : IN STD_LOGIC ; q : OUT STD_LOGIC ) ;END mux4_2 ;ARCHITECTURE rtl OF mux4_2 ISBEGINcmux4_2 : PROCESS ( cdata, sel, creset ) BEGIN IF ( creset = 1 ) THEN IF ( sel = 00 ) THEN - 多選擇的IF語句 q = cdata (0) ; ELSIF ( sel = 01 ) THEN q = cdata (1) ; ELSIF ( sel = 10 ) THEN q = cdata (2) ; ELSE q = cdata (3) ; END IF ; ELSE q = 0 ; END IF ; END PROCESS cmux4_2 ;END rtl ;【例4-14】 采用CASE語句來描述4選1選擇器的示例程序。（P76）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY mux4_3 ISPORT( cdata : IN STD_LOGIC_VECTOR ( 3 DOWNTO 0 ) ; sel : IN STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ; q : OUT STD_LOGIC ) ;END mux4_3 ;ARCHITECTURE rtl_mux4 OF mux4_3 ISSIGNAL temp_sel : INTEGER RANGE 0 TO 3 ;BEGINcmux4_3 : PROCESS ( cdata, sel ) BEGIN temp_sel = 0 ; IF ( sel (0) = 1 ) THEN - 選擇控制信號的譯碼 temp_sel = temp_sel + 1 ; END IF ; IF ( sel (1) = 1 ) THEN - 選擇控制信號的譯碼 temp_sel q q q q q q q q q q q q q q = XXXXXXXX ; END CASE ; ELSE q = 11111111 ; END IF ; END PROCESS ;END ARCHITECTURE rtl_cdecoder_3_8 ; - VHDL 1993版可以這么用【例4-16】 采用FOR LOOP語句實(shí)現(xiàn)32位奇偶校驗(yàn)電路的示例程序。（P78）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY cparity1 IS PORT( cdata : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 ) ; q : OUT STD_LOGIC ; qnot : OUT STD_LOGIC ) ;END ENTITY cparity1 ;ARCHITECTURE rtl_cparity OF cparity1 ISBEGINcparity_example : PROCESS ( cdata )VARIABLE temp : STD_LOGIC ; BEGIN temp : = 1 ; FOR i IN 0 TO 31 LOOP - FOR LOOP語句對32位邏輯值奇偶判斷 temp : = temp XOR cdata ( i ) ; END LOOP ; q = temp ; qnot = NOT temp ; END PROCESS cparity_example ;END ARCHITECTURE rtl_cparity ;【例4-17】 WHILE LOOP語句格式的示例程序。（79）VARIABLE sum_temp : INTEGER : = 0 ;VARIABLE i : INTEGER : = 0 ;BEGINsum_example : WHILE ( i 100 ) LOOP sum_temp : = sum_temp + i ; i : = i + 1 ; END LOOP sum_example ;END PROCESS ;【例4-18】 采用WHILE LOOP語句實(shí)現(xiàn)32位奇偶校驗(yàn)電路的示例程序。（80）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY cparity2 IS PORT( cdata : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 ) ; q : OUT STD_LOGIC ; qnot : OUT STD_LOGIC ) ;END ENTITY cparity2 ;ARCHITECTURE behav_cparity1 OF cparity2 ISBEGINcparity_example : PROCESS ( cdata )VARIABLE temp : STD_LOGIC ;VARIABLE i : INTEGER ; - 必須要有,不能省略 BEGIN temp : = 0 ; i : = 0 ; - WHILE LOOP語句對32位邏輯值進(jìn)行奇偶判斷 WHILE ( i 32 ) LOOP temp : = temp XOR cdata ( i ) ; i : = i + 1 ; END LOOP ; q = temp ; qnot = NOT temp ; END PROCESS cparity_example ;END ARCHITECTURE behav_cparity1 ;【例4-19】 采用外部信號控制的32位奇偶校驗(yàn)電路的示例程序。（81）LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL ;ENTITY cparity3 IS PORT( cdata : IN STD_LOGIC_VECTOR ( 31 DOWNTO 0 ) ; ccontrol : IN STD_LOGIC ; q : OUT STD_LOGIC ;qnot : OUT STD_LOGIC ) ;END ENTITY cparity3 ;ARCHITECTURE rtl_cparity OF cparity3 ISBEGINcparity_example : PROCESS ( cdata, ccontrol )VARIABLE temp : STD_LOGIC ; BEGIN temp : = 0 ; FOR i IN 0 TO 31 LOOP - FOR LOOP語句對32位邏輯值奇偶判斷 NEXT WHEN ccontrol = 0 ; - 外部信號ccontrol為邏輯低電平 temp : = temp XOR cdata ( i ) ; WAIT FOR 200 ms ; - 使得程序等待200 ms END LOOP ; q = temp ; qnot 150 THEN EXIT ; - 當(dāng)條件成立則提前退出循環(huán) END IF ; END LOOP ; END PROCESS cexit_example ;END ARCHITECTURE behav_cexit ;【例4-22】 采用RETURN語句的示例程序。（P83）FUNCTION cmax21 ( d1 : INTEGER ; d2 : INTEGER ) RETURN INTEGER ISVARIABLE temp : INTEGER : = 1 ; BEGIN IF d1 d2 THEN temp : = d1 ; ELSE temp : = d2 ; END IF ; RETURN temp ; END cmax21 ;【例4-23】 采用REPORT語句的示例程序。（P84）REPORT data0 is timed out at 0 - data0在邏輯0上超時(shí)SEVERITY ERROR ;REPORT q is not at 1 - q不在邏輯1電平上SEVERITY WARNING ;【例4-24】 使用NULL語句的示例程序。（P84）ARCHITECTURE dataflow OF cnull ISSIGNAL d, q : STD_LOGIC ;SIGNAL sel : STD_LOGIC_V