PCA9554_經(jīng)典資料

1、INTEGRATED CIRCUITSPCA9554/PCA9554A 8-bit I2C and SMBus I/O port with interruptProduct data2002 Jul 26Supersedes data of 2002 May 13P s on o sPhilips SemiconductorsProduct data8-bit I2C and SMBus I/O port with interruptPCA9554/PCA9554AFEATURESOperating power supply voltage range of 2.3 to 5.5 V5 V t

2、olerant I/OsPolarity inversion registerActive low interrupt outputLow stand-by currentNoise filter on SCL/SDA inputsNo glitch on power-upInternal power-on reset8 I/O pins which default to 8 inputs0 to 400 kHz clock frequencyESD protection exceeds 2000 V HBM per JESD22-A114,200 V MM per JESD22-A115 a

3、nd 1000 V CDM per JESD22-C101Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mAFour packages offered: SO16, SSOP16, TSSOP16, and HVQFN16DESCRIPTIONThe PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I

4、2C/SMBus applications and were developed to enhance the Philips family of IC I/O expanders. The improvements include higher drive capability, 5V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution

5、when additional I/O is needed for ACPI power switches, sensors, pushbuttons, LEDs, fans, etc.The PCA9554/54A consist of an 8-bit Configuration register (Input or Output selection); 8-bit Input register, 8-bit Output register and an8-bit Polarity inversion register (Active high or Active low operatio

6、n). The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion Register. All registe

7、rs can be read by the system master. Although pin to pin and I2C address compatible with the PCF8574 series, software changes are required due to the enhancements and are discussed in Application Note AN469.The PCA9554/54A open-drain interrupt output is activated when any input state differs from it

8、s corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine.Three hardware pins (A0, A1, A2) vary the fixed I2C address and allow up to e

9、ight devices to share the same I2C/SMBus. The PCA9554A is identical to the PCA9554 except that the fixed I2C address is different allowing up to sixteen of these devices (eight of each) on the same I2C/SMBus.ORDERING INFORMATIONPACKAGESTEMPERATUREORDER CODETOPSIDE MARKDRAWING NUMBERRANGE16-Pin Plast

10、ic SO (wide)40 to +85 CPCA9554DPCA9554DSOT162-116-Pin Plastic SSOP40 to +85 CPCA9554DB9554DBSOT338-116-Pin Plastic TSSOP40 to +85 CPCA9554PW9554DHSOT403-116-Pin Plastic HVQFN40 to +85 CPCA9554BS9554SOT629-116-Pin Plastic SO (wide)40 to +85 CPCA9554ADPCA9554ADSOT162-116-Pin Plastic SSOP40 to +85 CPCA

11、9554ADB9554ASOT338-116-Pin Plastic TSSOP40 to +85 CPCA9554APW9554ADHSOT403-116-Pin Plastic HVQFN40 to +85 CPCA9554ABS554ASOT629-1Standard packing quantities and other packaging data are available at /packaging.I2C is a trademark of Philips Semiconductors Corporation.SMBus as spec

12、ified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.2002 Jul 262853-2243 28672Philips SemiconductorsProduct data8-bit I2C and SMBus I/O port with interruptPCA9554/PCA9554APIN CONFIGURATION SO, SSOP, TSSOPPIN CONFIGURATION HVQFN1VDDA1A0VDDSDAA01616151413A121

13、5SDASCL3SCLA2112A214I/O0I/O0413INT211INTI/O1512I/O7I/O1310I/O7I/O2611I/O6I/O2I/O3710I/O549I/O6VSS89I/O45678I/O3VSSI/O4I/O5su01410TOP VIEWFigure 1. Pin configuration SO, SSOP, TSSOPsu01670Figure 2. Pin Configuration HVQFNPIN DESCRIPTIONSO. SSOP,HVQFNSYMBOLFUNCTIONTSSOP PINPINNUMBERNUMBER115A0Address

14、input 0216A1Address input 131A2Address input 24725I/O03I/O0 to I/O386VSSSupply ground9710I/O47I/O4 to I/O71311Interrupt output (open drain)INT1412SCLSerial clock line1513SDASerial data line1614VDDSupply voltageBLOCK DIAGRAMA0I/O0A1I/O1A2SCLI/O2INPUTI2C/SMBUS8-BITINPUT/I/O3SDAFILTEROUTPUTCONTROLPORTS

15、I/O4WRITE pulseI/O5READ pulseI/O6VDDI/O7POWER-ONVCCRESETVSSLPINTFILTERNOTE: ALL I/Os ARE SET TO INPUTS AT RESETSU01411Figure 3. Block diagram2002 Jul 263Philips SemiconductorsProduct data8-bit I2C and SMBus I/O port with interruptPCA9554/PCA9554AREGISTERSCommand ByteCommandProtocolFunction0Read byte

16、Input port register1Read/write byteOutput port register2Read/write bytePolarity inversion register3Read/write byteConfiguration registerThe command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers wil

17、l be written or read.Register 0 Input Port RegisterbitI7I6I5I4I3I2I1I0default11111111This register is a read only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect.Register

18、1 Output Port RegisterbitO7O6O5O4O3O2O1O0default11111111This register reflects the outgoing logic levels of the pins defined as outputs by Register 3. Bit values in this register have no effect on pins defined as inputs. Reads from this register return the value that is in the flip-flop controlling

19、the output selection, NOT the actual pin value.Register 2 Polarity Inversion RegisterbitN7N6N5N4N3N2N1N0default00000000This register allows the user to invert the polarity of the Input Port Register data. If a bit in this register is set (written with 1), the corresponding Input Port data is inverte

20、d. If a bit in this register is cleared (written with a 0), the Input Port data polarity is retained.Register 3 Configuration RegisterbitC7C6C5C4C3C2C1C0default11111111This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as

21、an input with high impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. At reset, the I/Os are configured as inputs with a weak pull-up to VDD.Power-on ResetWhen power is applied to VDD, an internal power-on reset holds the PCA9554 in a r

22、eset state until VDD has reached VPOR. At that point, the reset condition is released and the PCA9554 registers and state machine will initialize to their default states.Interrupt OutputThe open-drain interrupt output is activated when one of the port pins change state and the pin is configured as a

23、n input. The interrupt is deactivated when the input returns to its previous state or the input port register is read.Note that changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.2002 Jul 264P

24、hilips SemiconductorsProduct data8-bit I2C and SMBus I/O port with interruptPCA9554/PCA9554ASIMPLIFIED SCHEMATIC OF I/O0 TO I/O7DATA FROMSHIFT REGISTEROUTPUT PORT REGISTER DATACONFIGURATIONVDDREGISTERDATA FROMDQQ1SHIFT REGISTERFF100 kWWRITECKQDQCONFIGURATIONPULSEFFI/O0 TO I/O7WRITE PULSECKQOUTPUTQ2P

25、ORTREGISTERINPUT PORTVSSREGISTERDQINPUT PORTREGISTER DATAFFREAD PULSECKQTO INTDATA FROMDQPOLARITYSHIFT REGISTERFFREGISTER DATAWRITECKQPOLARITYPULSEPOLARITYINVERSIONREGISTERSU01472NOTE:At Power-on Reset, all registers return to default values.Figure 4. Simplified schematic of I/O0 to I/O7I/O portWhen

26、 an I/O is configured as an input, FETs Q1 and Q2 are off,creating a high impedance input with a weak pull-up (100 kW typ.) toVDD. The input voltage may be raised above VDD to a maximum of5.5 V.If the I/O is configured as an output, then either Q1 or Q2 is enabled,depending on the state of the outpu

27、t port register. Care should beexercised if an external voltage is applied to an I/O configured as anoutput because of the low impedance paths that exist between thepin and either VDD or VSS.2002 Jul 265Philips SemiconductorsProduct data8-bit I2C and SMBus I/O port with interruptPCA9554/PCA9554ADevi

28、ce addressSLAVE ADDRESSslave address0100110 A2 A1 A0 R/W1 A2 A1 A0 R/WFIXEDHARDWARE SELECTABLEfixedprogrammablesu01669su01418Figure 5. PCA9554 addressFigure 6. PCA9554A addressBus transactionsData is transmitted to the PCA9554/PCA9554A registers using the write mode as shown in Figures 7 and 8. Data

29、 is read from the PCA9554/PCA9554A registers using the read mode as shown in Figures 9 and 10. These devices do not implement an auto-increment function so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new command byte has been sent

30、.123456789SCLslave addresscommand bytedata to portSDAS 0100A2A1A00A 0000 000 1ADATA 1APstart conditionR/Wacknowledgeacknowledgeacknowledgefrom slavefrom slavefrom slaveWRITE TOPORTDATA OUTDATA 1 VALIDFROM PORTtpvsu01421Figure 7. WRITE to output port register123456789SCLslave addresscommand bytedata

31、to registerSDAS 0100A2A1A00A0000 00 1 1/0 ADATAA Pstart conditionR/Wacknowledgeacknowledgeacknowledgefrom slavefrom slavefrom slaveDATA TOREGISTERsu01422Figure 8. WRITE to configuration or polarity inversion registers2002 Jul 266Philips SemiconductorsProduct data8-bit I2C and SMBus I/O port with interruptPCA9554/PCA9554Aacknowledgeacknowledgeacknowledgeacknowledgeslave addressfrom slavefrom slave