數(shù)字電子鐘的VHDL程序設(shè)計(jì)實(shí)驗(yàn)報(bào)告

1、實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)項(xiàng)目名稱：數(shù)字電子鐘的vhdl程序設(shè)計(jì)實(shí)驗(yàn)項(xiàng)目性質(zhì)：普通試驗(yàn)所屬課程名稱：vhdl程序設(shè)計(jì)實(shí)驗(yàn)計(jì)劃學(xué)時(shí)：4學(xué)時(shí)一、 實(shí)驗(yàn)?zāi)康?掌握vhdl程序設(shè)計(jì)方法二、 實(shí)驗(yàn)內(nèi)容和要求能夠?qū)崿F(xiàn)小時(shí)（24進(jìn)制）、分鐘和秒鐘（60進(jìn)制）的計(jì)數(shù)功能具有復(fù)位功能功能擴(kuò)展：具有復(fù)位、整點(diǎn)報(bào)時(shí)提示、定時(shí)鬧鐘等功能在軟件工具平臺(tái)上，進(jìn)行vhdl語言的各模塊編程輸入、編譯實(shí)現(xiàn)和仿真驗(yàn)證。三、 實(shí)驗(yàn)主要儀器設(shè)備和材料 計(jì)算機(jī)四、 實(shí)驗(yàn)方法、步驟及結(jié)果測試數(shù)字電子鐘由計(jì)數(shù)器、比較器，寄存器和校時(shí)電路組成。振蕩器產(chǎn)生穩(wěn)定的高頻脈沖信號,作為數(shù)字鐘的時(shí)間基準(zhǔn),然后經(jīng)過分頻器輸出標(biāo)準(zhǔn)秒脈沖。秒計(jì)數(shù)器滿60后向分計(jì)數(shù)器進(jìn)位

2、,分計(jì)數(shù)器滿60后向小時(shí)計(jì)數(shù)器進(jìn)位,小時(shí)計(jì)數(shù)器按照“24翻1”規(guī)律計(jì)數(shù)。計(jì)數(shù)器的輸出分別經(jīng)譯碼器送顯示器顯示。1)時(shí)鐘產(chǎn)生電路。將開發(fā)板上的時(shí)鐘信號經(jīng)過分頻得到不同頻率的時(shí)鐘，分別作用于定時(shí)計(jì)數(shù)、led掃描。2)控制邏輯電路。完成電子鐘的系統(tǒng)邏輯控制，包括計(jì)時(shí)控制、時(shí)間校對、顯示掃描的邏輯控制，可完成系統(tǒng)復(fù)位、調(diào)整時(shí)間的功能。3)計(jì)時(shí)電路。主要按照時(shí)鐘模式完成計(jì)時(shí)功能。4)鬧鐘電路。通過輸入信號與電子鐘比較，輸出鬧鐘信號。各功能模塊的設(shè)計(jì)60進(jìn)制計(jì)數(shù)器設(shè)計(jì)秒數(shù)的計(jì)數(shù)以1hz的輸入clks為觸發(fā)信號，分?jǐn)?shù)的計(jì)數(shù)以秒數(shù)的進(jìn)位輸出作為觸發(fā)。是60進(jìn)制計(jì)數(shù)器器件圖形。接口： clks：1hz時(shí)鐘信號

3、outs：輸出顯示 res：復(fù)位信號 inmin：輸出十進(jìn)制信號每來一個(gè)clks上升沿，計(jì)數(shù)器就加1，當(dāng)計(jì)數(shù)器當(dāng)?shù)竭_(dá)第60個(gè)上升沿時(shí)，由59歸零，仿真符合60進(jìn)制計(jì)數(shù)器的要求。24進(jìn)制計(jì)數(shù)器設(shè)計(jì)24進(jìn)制計(jì)數(shù)器的結(jié)構(gòu)和原理與60進(jìn)制計(jì)數(shù)器相類似，只是將除以60改為除以24。下是生成的24進(jìn)制計(jì)數(shù)器器件圖形。接口： clkh：分的進(jìn)位信號 res：復(fù)位信號 outh：輸出十進(jìn)制的小時(shí)數(shù)每來一個(gè)clkh上升沿，計(jì)數(shù)器就加1，當(dāng)計(jì)數(shù)器當(dāng)?shù)竭_(dá)第24個(gè)上升沿時(shí)，outh由24歸零，仿真符合24進(jìn)制計(jì)數(shù)器的要求。整點(diǎn)報(bào)時(shí)及鬧鐘設(shè)計(jì)思路及原理圖當(dāng)計(jì)數(shù)時(shí)間在59分59秒時(shí)，報(bào)時(shí)模塊輸出報(bào)時(shí)控制信號。在報(bào)時(shí)設(shè)定時(shí)

4、間與計(jì)數(shù)信號相同時(shí)，鬧鐘控制信號輸出。接口： nzs1 nzm2 nzh1：時(shí)鐘計(jì)數(shù)信號 nzs2 nzm2 nzh2：設(shè)定鬧鐘信號 q：報(bào)時(shí)響鈴信號由圖可知，當(dāng)時(shí)鐘計(jì)數(shù)信號和設(shè)定鬧鐘信號相同時(shí)，報(bào)時(shí)響鈴信號q輸出。當(dāng)時(shí)鐘計(jì)數(shù)信號為零（整點(diǎn)）時(shí)，報(bào)時(shí)響鈴信號q輸出。頂層設(shè)計(jì)通過調(diào)用各模塊功能，得出如下仿真波形，證明設(shè)計(jì)成功，能夠完成鬧鐘功能及整點(diǎn)報(bào)時(shí)功能。接口：clk,res:輸入時(shí)鐘脈沖，復(fù)位信號 leds,ledm,ledh:時(shí)鐘顯示信號 nzs,nzm,nzh:輸入鬧鐘設(shè)置信號 qqq :響鈴信號程序代碼頂層程序文件library ieee;use ieee.std_logic_1164

5、.all;use ieee.std_logic_unsigned.all;entity clock isport(clk,res:in std_logic; leds,ledm,ledh:out std_logic_vector(5 downto 0); nzs,nzm,nzh:in std_logic_vector(5 downto 0); qqq :out std_logic); end clock;architecture behav of clock iscomponent sec port(clks: in std_logic; res1: in std_logic; inmin:o

6、ut std_logic; outs:out std_logic_vector(5 downto 0);end component;component minport(clkm: in std_logic; res2: in std_logic; inhour:out std_logic; outm:out std_logic_vector(5 downto 0);end component;component hourport(clkh: in std_logic; res3: in std_logic; outh:out std_logic_vector(5 downto 0);end c

7、omponent;component nzport(nzs1,nzs2,nzm1,nzm2,nzh1,nzh2:in std_logic_vector(5 downto 0); q :out std_logic);end component; signal s: std_logic_vector(5 downto 0);signal m: std_logic_vector(5 downto 0);signal h: std_logic_vector(5 downto 0);signal a: std_logic;signal b: std_logic;signal c: std_logic;b

8、eginu1 :sec port map(clks=clk,res1=res,inmin=a,outs=s);u2 :min port map(clkm=a,res2=res,inhour=b,outm=m);u3 :hour port map(clkh=b,res3=res,outh=h);u4:nzportmap(nzs1=s,nzm1=m,nzh1=h,nzs2=nzs,nzm2=nzm,nzh2=nzh,q=c);leds=s;ledh=h;ledm=m;qqq=c;end architecture behav;秒鐘計(jì)時(shí)模塊library ieee;use ieee.std_logic

9、_1164.all;use ieee.std_logic_unsigned.all;entity sec isport(clks: in std_logic; res: in std_logic; inmin:out std_logic; outs:out std_logic_vector(5 downto 0);end sec;architecture behav of sec issignal s1:std_logic_vector(5 downto 0);signal s2:std_logic;beginprocess(clks,res)beginif res =1 then s1=00

10、0000;s2=0;elsif clksevent and clks=1 then if s1111011 then s1=s1+1;s2=0; elsif s1=111011 then s1=000000;s2=1; end if;end if;inmin=s2;outs=s1;end process;end behav;分鐘計(jì)時(shí)模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity min isport(clkm: in std_logic; res: in std_logic; i

11、nhour:out std_logic; outm:out std_logic_vector(5 downto 0);end min;architecture behav of min issignal m1:std_logic_vector(5 downto 0):=111010;signal m2:std_logic;beginprocess(clkm,res)beginif res =1 then m1=000000;m2=0;elsif clkmevent and clkm=1 then if m1111011 then m1=m1+1;m2=0; elsif m1=111011 th

12、en m1=000000;m2=1; end if;end if;inhour=m2;outm=m1;end process;end behav;時(shí)鐘計(jì)時(shí)模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity hour isport(clkh: in std_logic; res: in std_logic; outh:out std_logic_vector(5 downto 0);end hour;architecture behav of hour issignal h1:std_

13、logic_vector(5 downto 0);beginprocess(clkh,res)beginif res =1 then h1=000000;elsif clkhevent and clkh=1 then if h1011000 then h1=h1+1; elsif h1=011000 then h1=000000; end if;end if;outh=h1;end process;end behav;鬧鐘及整點(diǎn)報(bào)時(shí)模塊library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity

14、nz isport(nzs1,nzs2,nzm1,nzm2,nzh1,nzh2:in std_logic_vector(5 downto 0); q :out std_logic);end nz;architecture behav of nz issignal qq:std_logic;beginprocess(nzs1,nzs2,nzm1,nzm2,nzh1,nzh2,qq)begin if (nzs1=nzs2 and nzm1=nzm2 and nzh1=nzh2)or (nzs1=000000and nzm1=000000) then qq=1; else qq=0; end if;q=qq;end process;end behav;總結(jié)本設(shè)計(jì)是用vhdl語言編寫編譯建模設(shè)計(jì)成的。由于初學(xué)vhdl語言，設(shè)計(jì)初期遇到了很多困難，在經(jīng)過一段時(shí)間的查閱資料以及老師的指導(dǎo)和同學(xué)之間的相互討論后完成了設(shè)計(jì)，但程序即使編譯成功仿真還是遇到了很多困難，比如不知道該如何進(jìn)行模塊例化