EDA技術(shù)與應(yīng)用講義-第3章-原理圖輸入設(shè)計(jì)方法-QUARTUS-II版本PPT課件

1、2021/6/71 第第3章章 原理圖輸入設(shè)計(jì)方法原理圖輸入設(shè)計(jì)方法 Quartus II 版操作版操作 課程講義課程講義 上一章 下一章 2021/6/72 本章內(nèi)容 v何時(shí)使用 原理圖設(shè)計(jì)輸入 v常用文件介紹 v設(shè)計(jì)步驟 v元件庫 和 Altera 宏的使用 v如何將VHDL代碼文件生成 圖形 符號 2021/6/73 何時(shí)使用 原理圖設(shè)計(jì)輸入 ？ v符合 傳統(tǒng)的 電路設(shè)計(jì) 習(xí)慣 v一般只是在 “top-level”(頂層)文件中使用？ 2021/6/74 Quartus II常用文件介紹 文件擴(kuò)展名稱用 途MAX+PLUS II 中的名稱 .vhdVHDL代碼源文件.vhd .bdf圖形

2、輸入源文件.gdf .qsf器件 引腳 與編譯配置指 配文件 .qsf .pofCPLD,EEPROM 器件 編程文件 .pof .sofFPGA器件的SRAM 文件 配置 .sof 2021/6/75 一般步驟 v電路的模塊劃分 v設(shè)計(jì)輸入 v器件和引腳指配 v編譯與排錯(cuò) v功能仿真和時(shí)序仿真 v編程與配置，設(shè)計(jì)代碼的芯片運(yùn)行 2021/6/76 電路的模塊劃分 v人工人工 根據(jù)電路功能 進(jìn)行 模塊劃分模塊劃分 v合理的模塊劃分 關(guān)系到 電路的性能 實(shí)現(xiàn)的難易程度 v根據(jù)模塊劃分和系統(tǒng)功能 確定確定： PLD芯片型號芯片型號 模塊劃分后，就可以進(jìn)行模塊劃分后，就可以進(jìn)行 具體設(shè)計(jì)具體設(shè)計(jì) 了

3、了 2021/6/77 設(shè)計(jì)輸入 一般EDA軟件允許3種設(shè)計(jì)輸入： HDL語言 電路圖 1.波形輸入 2021/6/78 圖形設(shè)計(jì)輸入的過程 + + 2021/6/79 圖形設(shè)計(jì):圖元 2021/6/710 圖形設(shè)計(jì):端口 2021/6/711 如何編寫一個(gè)新的圖形文件？ vFILE-NEW出現(xiàn)以下對話窗，選擇如下： 2021/6/712 如何調(diào)入元件？ vEdit-Insert Symbol 出現(xiàn)下面窗口 將將 自己編寫的自己編寫的 符號調(diào)入符號調(diào)入 從從 標(biāo)準(zhǔn)庫中標(biāo)準(zhǔn)庫中 調(diào)入調(diào)入 2021/6/713 將符號之間連線 2021/6/714 調(diào)入I/O端口元件符號 2021/6/715 2

4、類 標(biāo)準(zhǔn)庫 vMegafunctions/LPM 宏模塊 功能復(fù)雜、參數(shù)可設(shè)置的模塊 vPrimitives 基本圖元 簡單的、功能固定的邏輯元件，不可調(diào) 整參數(shù) 2021/6/716 如何將VHDL設(shè)計(jì)編程Symbol vVHDL文件編譯后，自動(dòng)生成同名的符號文件 v符號文件的擴(kuò)展名稱（*.bsf） v調(diào)入過程如下： 2021/6/717 何為 ？ 器件和引腳指配 v器件指配 F為設(shè)計(jì)輸入 選擇合適的PLD器件型號 v何謂引腳指配 F將設(shè)計(jì)代碼（圖形）中的端口（端口（PORT） 和 PLD芯片的引腳芯片的引腳 （PIN） 對應(yīng)起來的. v指配文件 FMAX+PLUS II： “ *.acf

5、” FQuartus II： “ *.qsf ” 2021/6/718 器件和引腳指配的方法 方法有2種 v在軟件的菜單界 面中指配 1.修改指配文件 （是文本文件） 2021/6/719 菜單界面中 指 配 2021/6/720 修改指配文件 vCHIP io_2d_lock vBEGIN v|iVD :INPUT_PIN = 7; v|iHD :INPUT_PIN = 8; v|iDENA :INPUT_PIN = 6; v|iCLK : INPUT_PIN = 211; v|oCLK : OUTPUT_PIN = 237; v|oVD :OUTPUT_PIN = 234; v|oHD :

6、 OUTPUT_PIN = 233; v|oDENA :OUTPUT_PIN = 235; v. vDEVICE = EPF10K30AQC240-2; vEND; v. 2021/6/721 編譯與排錯(cuò) 編譯過程有2種，作用分別為： 語法編譯：只是綜合并輸出網(wǎng)表 F編譯設(shè)計(jì)文件，綜合產(chǎn)生門級代碼 F編譯器只運(yùn)行到綜合這步就停止了 F編譯器只產(chǎn)生估算的延時(shí)數(shù)值 完全的編譯：包括編譯，網(wǎng)表輸出，綜合，配置器件 F編譯器除了完成以上的步驟，還要將設(shè)計(jì)配置到ALTERA的器件 中去 F編譯器根據(jù)器件特性產(chǎn)生真正的延時(shí)時(shí)間和給器件的配置文件 2021/6/722 功能仿真和時(shí)序仿真 v仿真的概念： 在

7、設(shè)計(jì)代碼下載到芯片前，在EDA軟件中對設(shè)計(jì)的輸 出進(jìn)行波形仿真。 v常用的2種仿真模式 v功能仿真 對設(shè)計(jì)的邏輯功能進(jìn)行仿真 v時(shí)序仿真 對設(shè)計(jì)的邏輯功能和信號的時(shí)間延時(shí)進(jìn)行仿真。 v仿真前還要做的工作 輸入信號的建立 Quartus II軟件中軟件中 關(guān)于仿真的原文關(guān)于仿真的原文 2021/6/723 2種 仿真文件 v矢量波形文件： v a Vector Waveform File (.vwf) v文本矢量文件 v a text-based Vector File (.vec), 2021/6/724 編程與配置 最后，最后， 如果仿真如果仿真 也正確也正確 的話，的話， 那我們就可以那我

8、們就可以 將設(shè)計(jì)代碼將設(shè)計(jì)代碼 配置或者編程配置或者編程 到到 芯片芯片 中了中了 v編程的文件類型 對于CPLD或者EPC2，ECS1等配置芯片，編程文件擴(kuò)展名為： “ *.POF “ v配置的文件類型 對于FPGA芯片，配置文件擴(kuò)展名為：“ *.SOF “ 2021/6/725 硬件設(shè)計(jì)和軟件設(shè)計(jì)的時(shí)間協(xié)調(diào) v軟件模塊劃分，器件的初步信號確定（主要 是根據(jù)需要的I/O引腳的數(shù)量） v軟件設(shè)計(jì)，硬件外圍電路設(shè)計(jì)和器件選擇 v軟件仿真 v仿真完成后，器件信號的重新審核，進(jìn)行硬 件電路圖設(shè)計(jì) v綜合調(diào)試 v完成 2021/6/726 設(shè)計(jì)的幾個(gè)問題 v如何組織多個(gè)設(shè)計(jì)文件的系統(tǒng)？，項(xiàng)目的概 念。

9、 v時(shí)鐘系統(tǒng)如何設(shè)計(jì)？ v電路的設(shè)計(jì)功耗 v高速信號的軟件和硬件設(shè)計(jì) 2021/6/727 The end. 2021/6/728 以下內(nèi)容以下內(nèi)容 為為 正文的引用，正文的引用， 可不閱讀?？刹婚喿x。 2021/6/729 常用EDA工具軟件 vEDA軟件方面，大體可以分為兩類： PLD器件廠商提供的EDA工具。較著名的如： vAltera公司的 Max+plus II和Quartus II、 vXilinx公司的Foundation Series、 vLatice-Vantis公司的ispEXERT System。 第三方專業(yè)軟件公司提供的EDA工具。常用的有： vSynopsys公司的F

10、PGA Compiler II、 vExemplar Logic公司的LeonardoSpectrum、 vSynplicity公司的Synplify。 1.第三方工具軟件是對CPLD/FPGA生產(chǎn)廠家開發(fā)軟件的補(bǔ) 充和優(yōu)化，如通常認(rèn)為Max+plus II和Quartus II對 VHDL/Verilog HDL邏輯綜合能力不強(qiáng)，如果采用專用的 HDL工具進(jìn)行邏輯綜合，會有效地提高綜合質(zhì)量。 2021/6/730 ALTERA 公司的公司的EDA合作伙伴合作伙伴 2021/6/731 硬件描述語言：起源 v是電子電路的文本描述。 v最早的發(fā)明者：美國國防部，美國國防部，VHDL,1983 v

11、大浪淘沙，為大者二： VHDL 和 Verilog HDL v其他的小兄弟： ABEL、AHDL、System Verilog、System C。 2021/6/732 一個(gè)D觸發(fā)器的VHDL代碼例子 v- VHDL code position: p83_ex4_11_DFF1 v- v- LIBARY IEEE; v- USE IEEE.STD_LOGIC_1164.ALL; vENTITY DFF1 IS vPORT (CLK:INBIT; vD:INBIT; vQ:OUTBIT v); vEND ENTITY DFF1; vARCHITECTURE bhv OF DFF1 IS vBEG

12、IN vPROCESS(CLK) vBEGIN vIF CLKEVENT AND (CLK=1) AND ( CLKLAST_VALUE = 0) THEN v- 嚴(yán)格的CLK信號上升沿定義 vQ 2021/6/738 Compiler Netlist Extractor （編譯器網(wǎng)表提取器）（編譯器網(wǎng)表提取器） vThe Compiler module that converts each design file in a project (or each cell of an EDIF Input File) into a separate binary CNF. The filename

13、(s) of the CNF(s) are based on the project name. Example vThe Compiler Netlist Extractor also creates a single HIF that documents the hierarchical connections between design files. vThis module contains a built-in EDIF Netlist Reader, Verilog Netlist Reader, VHDL Netlist Reader, and converters that

14、translate ADFs and SMFs for use with MAX+PLUS II. vDuring netlist extraction, this module checks each design file for problems such as duplicate node names, missing inputs and outputs, and outputs that are tied together. v返回 2021/6/739 Database Builder(數(shù)據(jù)庫構(gòu)建器 ): vThe Compiler module that builds a si

15、ngle, fully flattened project database that integrates all the design files in a project hierarchy. vThe Database Builder uses the HIF to link the CNFs that describe the project. Based on the HIF data, the Database Builder copies each CNF into the project database. Each CNF is inserted into the data

16、base as many times as it is used within the original hierarchical project. The database thus preserves the electrical connectivity of the project. vThe Compiler uses this database for the remainder of project processing. Each subsequent Compiler module updates the database until it contains the full

17、y optimized project. In the beginning, the database contains only the original netlists; at the end, it contains a fully minimized, fitted project, which the Assembler uses to create one or more files for device programming. vAs it creates the database, the Database Builder examines the logical comp

18、leteness and consistency of the project, and checks for boundary connectivity and syntactical errors (e.g., a node without a source or destination). Most errors are detected and can be easily corrected at this stage of project processing. v返回 2021/6/740 Logic Synthesizer vThe Compiler module that sy

19、nthesizes the logic in a projects design files. vUsing the database created by the Database Builder, the Logic Synthesizer calculates Boolean equations for each input to a primitive and minimizes the logic according to your specifications. vFor projects that use JK or SR flipflops, the Logic Synthes

20、izer checks each case to determine whether a D or T flipflop will implement the project more efficiently. D or T flipflops are substituted where appropriate, and the resulting equations are minimized accordingly. vThe Logic Synthesizer also synthesizes equations for flipflops to implement state regi

21、sters of state machines. An equation for each state bit is optimally implemented with either a D or T flipflop. If no state bit assignments have been made, or if an incomplete set of state bit assignments has been created, the Logic Synthesizer automatically creates a set of state bits to encode the

22、 state machine. These encodings are chosen to minimize the resources used. v返回 2021/6/741 Fitter（適配器） vThe Compiler module that fits the logic of a project into one or more devices. vUsing the database updated by the Partitioner, the Fitter matches the logic requirements of the project with the avai

23、lable resources of one or more devices. It assigns each logic function to the best logic cell location and selects appropriate interconnection paths and pin assignments. vThe Fitter attempts to match any resource assignments made for the project with the resources on the device. If it cannot find a

24、fit, the Fitter allows you to override some or all of your assignments or terminate compilation. vThe Fitter module generates a Fit File that documents pin, buried logic cell, chip, clique, and device assignments made by the Fitter module in the last successful compilation. Each time the project com

25、piles successfully, the Fit File is overwritten. You can back- annotate the assignments in the file to preserve them in future compilations. v返回 2021/6/742 Timing SNF Extractor(時(shí)序SNF文件提取器) vThe Compiler module that creates a timing SNF containing the logic and timing information required for timing

26、simulation, delay prediction, and timing analysis. vThe Timing SNF Extractor is turned on with the Timing SNF Extractor command (Processing menu). It is also turned on automatically when you turn on the EDIF Netlist Writer, Verilog Netlist Writer, or VHDL Netlist Writer command (Interfaces menu). Th

27、e Timing SNF Extractor cannot be turned on at the same time as the Functional SNF Extractor or the Linked SNF Extractor. vA timing SNF describes the fully optimized circuit after all logic synthesis and fitting have been completed. Regardless of whether a project is partitioned into multiple devices

28、, the timing SNF describes a project as a whole. Therefore, timing simulation and timing analysis (including delay prediction) are available only for the project as a whole. Neither timing simulation nor functional testing is available for individual devices in a multi-device project. Functional tes

29、ting is available only for a single-device project. v返回 2021/6/743 Assembler（匯編器） vThe Compiler module that creates one or more programming files for programming or configuring the device(s) for a project. vThe Assembler module completes project processing by converting the Fitters device, logic cel

30、l, and pin assignments into a programming image for the device(s), in the form of one or more POFs, SOFs, Hex Files, TTFs, Jam Files, JBC Files, and/or JEDEC Files. POFs and JEDEC Files are always generated; SOFs, Hex Files, and TTFs are always generated if the project uses ACEX 1K, FLEX 6000, FLEX

31、8000 or FLEX 10K devices; and Jam Files and JBC Files are always generated for MAX 9000, MAX 7000B, MAX 7000AE or MAX 3000A projects. If you turn on the Enable JTAG Support option in the Classic & MAX Global Project Device Options dialog box (Assign menu) or the Classic & MAX Individual Device Optio

32、ns dialog box, the Assembler will also generate Jam Files and JBC Files for MAX 7000A or MAX 7000S projects. After compilation, you can also use SOFs to create different types of files for configuring FLEX 6000, FLEX 8000 and FLEX 10K devices with Convert SRAM Object Files (File menu). vThe programm

33、ing files can then be processed by the MAX+PLUS II Programmer and the MPU or APU hardware to produce working devices. Several other programming hardware manufacturers also provide programming support for Altera devices. v返回 2021/6/744 Simulation Mode vFunctional Simulates the behavior of flattened n

34、etlists extracted from the design files. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec), although the Simulator uses only the sequence of logic level cha

35、nges, and not their timing, from the vector stimuli. This type of simulation also allows you to check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist). vTiming Uses a fully compile

36、d netlist that includes estimated or actual timing information. You can use Tcl commands and scripts to control simulation and to provide vector stimuli. You can also provide vector stimuli in a Vector Waveform File (.vwf) or a text-based Vector File (.vec). This type of simulation also allows you t

37、o check setup and hold times, detect glitches, and check simulation coverage (the ratio of output ports actually toggling between 1 and 0 during simulation, compared to the total number of output ports present in the netlist). vTiming using Fast Timing Model Performs a timing simulation using the Fa

38、st Timing Model to simulate fastest possible timing conditions with the fastest device speed grade 2021/6/745 Megafunctions/LPM vArithmetic Components vGates vI/O Components vMemory Compiler vParallel Flash Loader Megafunction vSignalTap II Logic Analyzer Megafunction 1.Storage Components 2021/6/746

39、 Arithmetic Components valtaccumulate divide* valtfp_add_sub lpm_abs valtfp_mult lpm_add_sub valtmemmult lpm_compare valtmult_accum lpm_counter valtmult_add lpm_divide valtsqrt lpm_mult 1.altsquare parallel_add 2021/6/747 Gates vbusmuxlpm_inv vlpm_andlpm_mux vlpm_bustri lpm_or vlpm_clshift lpm_xor vlpm_constant mux vlpm_decode 2021/6/748 I/O Components valtcdr_rxaltdqs valtcdr_tx altgxb valtclkctrl altlvds_rx valtclklock altlvds_tx valtddio_bidir altpll valtddio_in altpll_reconfig valtddio_out altremote_update valtdq altufm_osc v 2021/6/749 Memory Compiler valtcsmem