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1、 本科實(shí)驗(yàn)報(bào)告實(shí)驗(yàn)名稱(chēng): vhdl語(yǔ)言及集成電路設(shè)計(jì)實(shí)驗(yàn) 課程名稱(chēng):vhdl語(yǔ)言及集成電路設(shè)計(jì)實(shí)驗(yàn)時(shí)間:2014.5任課教師:桂小琰實(shí)驗(yàn)地點(diǎn):4-427實(shí)驗(yàn)教師:任仕偉實(shí)驗(yàn)類(lèi)型: 原理驗(yàn)證 綜合設(shè)計(jì) 自主創(chuàng)新學(xué)生姓名:學(xué)號(hào)/班級(jí):組 號(hào):學(xué) 院:信息與電子學(xué)院同組搭檔:專(zhuān) 業(yè):電子科學(xué)與技術(shù)成 績(jī):實(shí)驗(yàn)一:帶有異步復(fù)位端的d觸發(fā)器一、實(shí)驗(yàn)?zāi)康模?)熟悉linux操作環(huán)境和modelsim軟件環(huán)境(2)理解時(shí)序邏輯和組合邏輯電路的區(qū)別(3)理解并行語(yǔ)句和順序語(yǔ)句(4)用vhdl語(yǔ)言編寫(xiě)一個(gè)帶有異步復(fù)位端的d觸發(fā)器及其測(cè)試文件二、實(shí)驗(yàn)原理(1)組合邏輯和時(shí)序邏輯組合邏輯電路當(dāng)前輸出的值僅取決于當(dāng)前

2、的輸入,不需要觸發(fā)器等具有存儲(chǔ)能力的邏輯單元,僅僅使用組合邏輯門(mén)時(shí)序邏輯電路的當(dāng)前輸出不僅取決于當(dāng)前的輸入,還與以前的輸入有關(guān),這類(lèi)電路中包括寄存器等元件,也包括組合邏輯電路,寄存器通過(guò)一個(gè)反饋環(huán)和組合邏輯模塊相連。觸發(fā)器便是屬于時(shí)序邏輯電路(2)并行和順序代碼從本質(zhì)上講,vhdl代碼是并發(fā)執(zhí)行的。只有process,function或procedure內(nèi)的代碼才是順序執(zhí)行的。當(dāng)它們作為一個(gè)整體時(shí),與其他模塊之間又是并發(fā)執(zhí)行的。以下是3個(gè)并發(fā)描述語(yǔ)句(stat1,stat2和stat3)的代碼,會(huì)產(chǎn)生同樣的電路結(jié)構(gòu)。stat1 stat3 stat1stat2 = stat2 = stat3

3、= 其他排列順序stat3 stat1 stat2(3)并行語(yǔ)句進(jìn)程(process) 語(yǔ)法結(jié)構(gòu):進(jìn)程名: process (敏感信號(hào)列表)變量說(shuō)明語(yǔ)句begin(順序執(zhí)行的代碼)end process 進(jìn)程名; process 的特點(diǎn)1多進(jìn)程之間是并行執(zhí)行的;2進(jìn)程結(jié)構(gòu)內(nèi)部的所有語(yǔ)句都是順序執(zhí)行的;3進(jìn)程中可訪問(wèn)結(jié)構(gòu)體或?qū)嶓w中所定義的信號(hào);4進(jìn)程的啟動(dòng)是由敏感信號(hào)列表所標(biāo)明的信號(hào)來(lái)觸發(fā),也可以用wait語(yǔ)句等待一個(gè)觸發(fā)條件的成立。5各進(jìn)程之間的通信是由信號(hào)來(lái)傳遞的。(4)帶有異步復(fù)位端的d觸發(fā)器 電路符號(hào) 功能表rdcpq0xx01x0保持1x1保持10上升沿011上升沿1三、實(shí)驗(yàn)代碼lib

4、rary ieee;use ieee.std_logic_1164.all;entity dff isport(d,clk,rst:in std_logic; q:out std_logic);end dff; architecture behavior of dff is begin process(rst,clk) begin if(rst=1) then q=0; elsif(clkevent and clk=1) then qd,clk=clk,rst=rst,q=q); clk_gen:process begin clk=0; wait for clk_period/2; clk=1

5、; wait for clk_period/2; end process; d_gen:process begin wait for 100 ns; d=1; wait for 100 ns; d=0; end process; rst_gen:process begin rst=1; wait for 150 ns; rst=0; wait for 500 ns; rst=1; wait for 150 ns; wait; end process;end tb_behavior;四、仿真結(jié)果實(shí)驗(yàn)二 步進(jìn)電機(jī)控制器一、實(shí)驗(yàn)?zāi)康模?)理解兩種狀態(tài)機(jī)的區(qū)別(2)熟悉兩種編程風(fēng)格(3)編寫(xiě)bcd計(jì)數(shù)

6、器和步進(jìn)電機(jī)二、實(shí)驗(yàn)原理(1)米里型狀態(tài)機(jī)和摩爾型狀態(tài)機(jī)米里(mealy)型狀態(tài)機(jī):狀態(tài)機(jī)的輸出信號(hào)不僅與電路的當(dāng)前狀態(tài)有關(guān),還與當(dāng)前的輸入有關(guān)摩爾(moore)型狀態(tài)機(jī):狀態(tài)機(jī)的當(dāng)前輸出僅僅由當(dāng)前狀態(tài)決定(2)有限狀態(tài)機(jī)設(shè)計(jì)流程:1 理解問(wèn)題背景。2 邏輯抽象,得出狀態(tài)轉(zhuǎn)移圖。3 狀態(tài)簡(jiǎn)化。4 狀態(tài)分配。5 用vhdl來(lái)描述有限狀態(tài)機(jī)。(3)bcd計(jì)數(shù)器原理圖(4)步進(jìn)電機(jī)控制器原理圖步進(jìn)電機(jī)狀態(tài)與輸出信號(hào)的對(duì)應(yīng)關(guān)系狀態(tài)輸出狀態(tài)s0s1s2s30001001001001000三、實(shí)驗(yàn)代碼(1)bcd計(jì)數(shù)器library ieee;use ieee.std_logic_1164.all;ent

7、ity counter is port(clk,rst:in std_logic;count:out std_logic_vector(3 downto 0);end counter;architecture state_machine of counter istype state is(zero,one,two,three,four,five,six,seven,eight,nine);signal pr_state,nx_state:state;begin process (rst,clk) begin if(rst=1)then pr_state count =0000; nx_sta

8、te count =0001; nx_state count =0010; nx_state count =0011; nx_state count =0100; nx_state count =0101; nx_state count =0110; nx_state count =0111; nx_state count =1000; nx_state count =1001; nx_state = zero; end case; end process; end state_machine; (2)步進(jìn)電機(jī)控制器library ieee;use ieee.std_logic_1164.al

9、l;entity stepmotor is port(clk,rst,x:in std_logic;output:out std_logic_vector(3 downto 0);end stepmotor;architecture state_machine of stepmotor istype state is(s0,s1,s2,s3);signal pr_state,nx_state:state;begin process (clk,rst) begin if(rst=1)then pr_state=s0; elsif(clk event and clk =1)then pr_stat

10、e output =0001; nx_state output =0010; nx_state output =0100; nx_state output =1000; nx_state output =0001; nx_state output =0010; nx_state output =0100; nx_state output =1000; nx_state = s0; end case; end if; end process; end state_machine;四、仿真結(jié)果bcd計(jì)數(shù)器步進(jìn)電機(jī)控制器實(shí)驗(yàn)三 十六位加法器設(shè)計(jì)一、實(shí)驗(yàn)?zāi)康模?)掌握元件例化的方法(2)理解for/g

11、enerate語(yǔ)句的用法(3)編程完成4位加法器和16位加法器的設(shè)計(jì)二、實(shí)驗(yàn)原理(1)元件的例化元件聲明是對(duì)vhdl模塊(即底層設(shè)計(jì),也是完整的vhdl設(shè)計(jì))的說(shuō)明,使之可在其他被調(diào)用,元件聲明可放在程序包中,也可在某個(gè)設(shè)計(jì)的構(gòu)造體中聲明。元件例化指元件的調(diào)用。元件聲明及元件例化的語(yǔ)法分別如下:元件聲明:component元件實(shí)體名prot(元件端口信息,同該元件實(shí)現(xiàn)時(shí)的實(shí)體的port部分);endcompnent;元件例化:例化名:實(shí)體名,即元件名portmap(端口列表);(2)生成語(yǔ)句(generate)generate語(yǔ)句用于循環(huán)執(zhí)行某項(xiàng)操作。for模式的生成語(yǔ)句主要用于相同結(jié)構(gòu)的描述

12、中;for模式語(yǔ)法結(jié)構(gòu):for/generate:標(biāo)號(hào):for 變量in 離散區(qū)間generate(并行處理語(yǔ)句);end generate;(3)16位加法器的設(shè)計(jì)三、實(shí)驗(yàn)代碼4位加法器:library ieee;use ieee.std_logic_1164.all;entity adder4 is port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(3 downto 0); cout:out std_logic);end adder4;architecture behav o

13、f adder4 issignal c: std_logic_vector(4 downto 0);signal p: std_logic_vector(3 downto 0);signal g: std_logic_vector(3 downto 0);begin g1:for i in 0 to 3 generate p(i)=a(i) xor b(i); g(i)=a(i) and b(i); s(i)=p(i) xor c(i);end generate;c(0)=cin;c(1)=(cin and p(0) or g(0);c(2)=(cin and p(0) and p(1) or

14、 (g(0) and p(1) or g(1);c(3)=(cin and p(0) and p(1)and p(2) or (g(0) and p(1) and p(2) or (g(1) and p(2) or g(2);c(4)=(cin and p(0) and p(1)and p(2) and p(3) or (g(0) and p(1) and p(2) and p(3) or (g(1) and p(2) and p(3) or (g(2) and p(3) or g(3);couta,b=b,s=s,cin=cin,cout=cout ); processbegin a=x00

15、00; b=x0000; cin=1; wait for 100ns; a=0000100000000001; b=0100000000000111; cin=0; wait for 100ns; a=x1111; b=x1111; cin=1; wait for 100ns; a=0000100000000001; b=1110000000000111; cin=1; wait ; end process;end behav;四、仿真結(jié)果實(shí)驗(yàn)四 選擇運(yùn)算器一、實(shí)驗(yàn)?zāi)康模海?)對(duì)前幾次實(shí)驗(yàn)用到的知識(shí)進(jìn)行總結(jié)(2)綜合運(yùn)用理論課上的知識(shí),完成選擇運(yùn)算器的設(shè)計(jì)二、實(shí)驗(yàn)原理(1)設(shè)計(jì)要求:輸出信號(hào):

16、一個(gè)cout(15:0) ,16位乘法器:要求用部分積實(shí)現(xiàn)加法器:8位加法器,高7位補(bǔ)零完成比較器、乘法器、加法器的設(shè)計(jì),不可以直接使用+,x運(yùn)算符直接實(shí)現(xiàn)。(2)選擇器運(yùn)算器總原理圖如下:(3)乘法器部分采用并行乘法器(4)加法器:8位加法器的設(shè)計(jì)和上一個(gè)試驗(yàn)類(lèi)似,先設(shè)計(jì)一個(gè)4位加法器,進(jìn)而編譯8位加法器。三、實(shí)驗(yàn)代碼與門(mén):library ieee;use ieee.std_logic_1164.all;entity and_2 is port(a,b:in std_logic; y:out std_logic);end and_2;architecture behav of and_2 i

17、sbegin y= a and b;end behav; 全加器:library ieee;use ieee.std_logic_1164.all;entity fau is port(a,b,cin:in std_logic; s,cout:out std_logic);end fau;architecture behav of fau isbegin s=a xor b xor cin; cout=(a and b)or(a and cin)or(b and cin); end behav;頂層:library ieee;use ieee.std_logic_1164.all;use wo

18、rk.my_components.all;entity top_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end top_row;architecture behav of top_row isbegin u1:component and_2 port map(a,b(7),sout(6); u2:component and_2 port map(a,b(6),sout(5); u3:co

19、mponent and_2 port map(a,b(5),sout(4); u4:component and_2 port map(a,b(4),sout(3); u5:component and_2 port map(a,b(3),sout(2); u6:component and_2 port map(a,b(2),sout(1); u7:component and_2 port map(a,b(1),sout(0); u8:component and_2 port map(a,b(0),p); u9:for i in 0 to 6 generate cout(i)=0; end gen

20、erate;end behav;中層:library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity mid_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sin,cin:in std_logic_vector(6 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end mid_row;architecture behav of mi

21、d_row issignal and_out:std_logic_vector(6 downto 0);begin u1:component and_2 port map(a,b(7),sout(6); u2:component and_2 port map(a,b(6),and_out(6); u3:component and_2 port map(a,b(5),and_out(5); u4:component and_2 port map(a,b(4),and_out(4); u5:component and_2 port map(a,b(3),and_out(3); u6:compone

22、nt and_2 port map(a,b(2),and_out(2); u7:component and_2 port map(a,b(1),and_out(1); u8:component and_2 port map(a,b(0),and_out(0); u9:component fau port map(sin(6),cin(6),and_out(6),sout(5),cout(6); u10:component fau port map(sin(5),cin(5),and_out(5),sout(4),cout(5); u11:component fau port map(sin(4

23、),cin(4),and_out(4),sout(3),cout(4); u12:component fau port map(sin(3),cin(3),and_out(3),sout(2),cout(3); u13:component fau port map(sin(2),cin(2),and_out(2),sout(1),cout(2); u14:component fau port map(sin(1),cin(1),and_out(1),sout(0),cout(1); u15:component fau port map(sin(0),cin(0),and_out(0),p,co

24、ut(0); end behav;底層:library ieee;use ieee.std_logic_1164.all;use work.my_components.all;entity lower_row is port(sin,cin:in std_logic_vector(6 downto 0); p:out std_logic_vector(7 downto 0);end lower_row;architecture behav of lower_row is signal local:std_logic_vector(6 downto 0);beginlocal(0)=0;u1:c

25、omponent fau port map(sin(0),cin(0),local(0),p(0),local(1); u2:component fau port map(sin(1),cin(1),local(1),p(1),local(2); u3:component fau port map(sin(2),cin(2),local(2),p(2),local(3); u4:component fau port map(sin(3),cin(3),local(3),p(3),local(4);u5:component fau port map(sin(4),cin(4),local(4),

26、p(4),local(5); u6:component fau port map(sin(5),cin(5),local(5),p(5),local(6); u7:component fau port map(sin(6),cin(6),local(6),p(6),p(7); end behav;乘法器用到的的元件聲明:library ieee;use ieee.std_logic_1164.all;package my_components is component and_2 is port(a,b:in std_logic; y:out std_logic); end component

27、; component fau is port(a,b,cin:in std_logic; s,cout:out std_logic); end component; component top_row is port(a:in std_logic; b:in std_logic_vector(7 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end component; component mid_row is port(a:in std_logic; b:in std_logic_vecto

28、r(7 downto 0); sin,cin:in std_logic_vector(6 downto 0); sout,cout:out std_logic_vector(6 downto 0); p:out std_logic); end component; component lower_row is port(sin,cin:in std_logic_vector(6 downto 0); p:out std_logic_vector(7 downto 0); end component; end my_components;乘法器:library ieee;use ieee.std

29、_logic_1164.all;use work.my_components.all;entity multiplier is port(a,b:in std_logic_vector(7 downto 0); prod:out std_logic_vector(15 downto 0);end multiplier;architecture behav of multiplier istype matrix is array (0 to 7) of std_logic_vector(6 downto 0);signal s,c:matrix;beginu1:component top_row

30、 port map(a(0),b,s(0),c(0),prod(0);u2:component mid_row port map(a(1),b,s(0),c(0),s(1),c(1),prod(1);u3:component mid_row port map(a(2),b,s(1),c(1),s(2),c(2),prod(2);u4:component mid_row port map(a(3),b,s(2),c(2),s(3),c(3),prod(3);u5:component mid_row port map(a(4),b,s(3),c(3),s(4),c(4),prod(4);u6:co

31、mponent mid_row port map(a(5),b,s(4),c(4),s(5),c(5),prod(5);u7:component mid_row port map(a(6),b,s(5),c(5),s(6),c(6),prod(6);u8:component mid_row port map(a(7),b,s(6),c(6),s(7),c(7),prod(7);u9:component lower_row port map(s(7),c(7),prod(15 downto 8);end behav;4位加法器:library ieee;use ieee.std_logic_11

32、64.all;entity adder4 is port(a,b:in std_logic_vector(3 downto 0); cin:in std_logic; s:out std_logic_vector(3 downto 0); cout:out std_logic);end adder4;architecture behav of adder4 issignal c: std_logic_vector(4 downto 0);signal p: std_logic_vector(3 downto 0);signal g: std_logic_vector(3 downto 0);b

33、egin g1:for i in 0 to 3 generate p(i)=a(i) xor b(i); g(i)=a(i) and b(i); s(i)=p(i) xor c(i);end generate;c(0)=cin;c(1)=(cin and p(0) or g(0);c(2)=(cin and p(0) and p(1) or (g(0) and p(1) or g(1);c(3)=(cin and p(0) and p(1)and p(2) or (g(0) and p(1) and p(2) or (g(1) and p(2) or g(2);c(4)=(cin and p(0) and p(1)and p(2) and p(3) o

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